src/soc/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  21                                     SV64P_PID_SIZE, SVP64RMFields,
  22                                     SVP64RM_EXTRA2_SPEC_SIZE,
  23                                     SVP64RM_EXTRA3_SPEC_SIZE,
  24                                     SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
  25                                     SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
  26                                     SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
  27                                     SVP64RM_ELWIDTH_SIZE)
  28 from soc.decoder.pseudo.pagereader import ISA
  29 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  30 from soc.decoder.selectable_int import SelectableInt
  31
  32
  33 # decode GPR into sv extra
  34 def  get_extra_gpr(etype, regmode, field):
  35     if regmode == 'scalar':
  36         # cut into 2-bits 5-bits SS FFFFF
  37         sv_extra = field >> 5
  38         field = field & 0b11111
  39     else:
  40         # cut into 5-bits 2-bits FFFFF SS
  41         sv_extra = field & 0b11
  42         field = field >> 2
  43     return sv_extra, field
  44
  45
  46 # decode 3-bit CR into sv extra
  47 def  get_extra_cr_3bit(etype, regmode, field):
  48     if regmode == 'scalar':
  49         # cut into 2-bits 3-bits SS FFF
  50         sv_extra = field >> 3
  51         field = field & 0b111
  52     else:
  53         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  54         sv_extra = field & 0b1111
  55         field = field >> 4
  56     return sv_extra, field
  57
  58
  59 # decodes SUBVL
  60 def decode_subvl(encoding):
  61     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  62     assert encoding in pmap, \
  63         "encoding %s for SUBVL not recognised" % encoding
  64     return pmap[encoding]
  65
  66
  67 # decodes elwidth
  68 def decode_elwidth(encoding):
  69     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  70     assert encoding in pmap, \
  71         "encoding %s for elwidth not recognised" % encoding
  72     return pmap[encoding]
  73
  74
  75 # decodes predicate register encoding
  76 def decode_predicate(encoding):
  77     pmap = { # integer
  78             '1<<r3': (0, 0b001),
  79             'r3'   : (0, 0b010),
  80             '~r3'   : (0, 0b011),
  81             'r10'   : (0, 0b100),
  82             '~r10'  : (0, 0b101),
  83             'r30'   : (0, 0b110),
  84             '~r30'  : (0, 0b111),
  85             # CR
  86             'lt'    : (1, 0b000),
  87             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  88             'gt'    : (1, 0b010),
  89             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  90             'eq'    : (1, 0b100),
  91             'ne'    : (1, 0b101),
  92             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
  93             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
  94            }
  95     assert encoding in pmap, \
  96         "encoding %s for predicate not recognised" % encoding
  97     return pmap[encoding]
  98
  99
 100 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 101 def decode_bo(encoding):
 102     pmap = { # TODO: double-check that these are the same as Branch BO
 103             'lt'    : 0b000,
 104             'nl'    : 0b001, 'ge'    : 0b001, # same value
 105             'gt'    : 0b010,
 106             'ng'    : 0b011, 'le'    : 0b011, # same value
 107             'eq'    : 0b100,
 108             'ne'    : 0b101,
 109             'so'    : 0b110, 'un'    : 0b110, # same value
 110             'ns'    : 0b111, 'nu'    : 0b111, # same value
 111            }
 112     assert encoding in pmap, \
 113         "encoding %s for BO Mode not recognised" % encoding
 114     return pmap[encoding]
 115
 116 # partial-decode fail-first mode
 117 def decode_ffirst(encoding):
 118     if encoding in ['RC1', '~RC1']:
 119         return encoding
 120     return decode_bo(encoding)
 121
 122
 123 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 124 class SVP64Asm:
 125     def __init__(self, lst):
 126         self.lst = lst
 127         self.trans = self.translate(lst)
 128
 129     def __iter__(self):
 130         yield from self.trans
 131
 132     def translate(self, lst):
 133         isa = ISA() # reads the v3.0B pseudo-code markdown files
 134         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 135         for insn in lst:
 136             # find first space, to get opcode
 137             ls = insn.split(' ')
 138             opcode = ls[0]
 139             # now find opcode fields
 140             fields = ''.join(ls[1:]).split(',')
 141             fields = list(map(str.strip, fields))
 142             print ("opcode, fields", ls, opcode, fields)
 143
 144             # identify if is a svp64 mnemonic
 145             if not opcode.startswith('sv.'):
 146                 yield insn  # unaltered
 147                 continue
 148             opcode = opcode[3:] # strip leading "sv."
 149
 150             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 151             opmodes = opcode.split("/") # split at "/"
 152             v30b_op = opmodes.pop(0)    # first is the v3.0B
 153             # check instruction ends with dot
 154             rc_mode = v30b_op.endswith('.')
 155             if rc_mode:
 156                 v30b_op = v30b_op[:-1]
 157
 158             if v30b_op not in isa.instr:
 159                 raise Exception("opcode %s of '%s' not supported" % \
 160                                 (v30b_op, insn))
 161             if v30b_op not in svp64.instrs:
 162                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 163                                 (v30b_op, insn))
 164             v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
 165             rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 166             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 167             print ("v3.0B regs", opcode, v30b_regs)
 168             print (rm)
 169
 170             # right.  the first thing to do is identify the ordering of
 171             # the registers, by name.  the EXTRA2/3 ordering is in
 172             # rm['0']..rm['3'] but those fields contain the names RA, BB
 173             # etc.  we have to read the pseudocode to understand which
 174             # reg is which in our instruction. sigh.
 175
 176             # first turn the svp64 rm into a "by name" dict, recording
 177             # which position in the RM EXTRA it goes into
 178             # also: record if the src or dest was a CR, for sanity-checking
 179             # (elwidth overrides on CRs are banned)
 180             decode = decode_extra(rm)
 181             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 182             svp64_reg_byname = {}
 183             svp64_reg_byname.update(svp64_src)
 184             svp64_reg_byname.update(svp64_dest)
 185
 186             print ("EXTRA field index, by regname", svp64_reg_byname)
 187
 188             # okaaay now we identify the field value (opcode N,N,N) with
 189             # the pseudo-code info (opcode RT, RA, RB)
 190             assert len(fields) == len(v30b_regs), \
 191                 "length of fields %s must match insn `%s`" % \
 192                         (str(v30b_regs), insn)
 193             opregfields = zip(fields, v30b_regs) # err that was easy
 194
 195             # now for each of those find its place in the EXTRA encoding
 196             extras = OrderedDict()
 197             for idx, (field, regname) in enumerate(opregfields):
 198                 extra = svp64_reg_byname.get(regname, None)
 199                 regtype = get_regtype(regname)
 200                 extras[extra] = (idx, field, regname, regtype)
 201                 print ("    ", extra, extras[extra])
 202
 203             # great! got the extra fields in their associated positions:
 204             # also we know the register type. now to create the EXTRA encodings
 205             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 206             ptype = rm['Ptype'] # Predication type: Twin / Single
 207             extra_bits = 0
 208             v30b_newfields = []
 209             for extra_idx, (idx, field, regname, regtype) in extras.items():
 210                 # is it a field we don't alter/examine?  if so just put it
 211                 # into newfields
 212                 if regtype is None:
 213                     v30b_newfields.append(field)
 214
 215                 # first, decode the field number. "5.v" or "3.s" or "9"
 216                 field = field.split(".")
 217                 regmode = 'scalar' # default
 218                 if len(field) == 2:
 219                     if field[1] == 's':
 220                         regmode = 'scalar'
 221                     elif field[1] == 'v':
 222                         regmode = 'vector'
 223                 field = int(field[0]) # actual register number
 224                 print ("    ", regmode, field, end=" ")
 225
 226                 # see Mode field https://libre-soc.org/openpower/sv/svp64/
 227                 # XXX TODO: the following is a bit of a laborious repeated
 228                 # mess, which could (and should) easily be parameterised.
 229                 # XXX also TODO: the LD/ST modes which are different
 230                 # https://libre-soc.org/openpower/sv/ldst/
 231
 232                 # encode SV-GPR field into extra, v3.0field
 233                 if regtype == 'GPR':
 234                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 235                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 236                     # (and shrink to a single bit if ok)
 237                     if etype == 'EXTRA2':
 238                         if regmode == 'scalar':
 239                             # range is r0-r63 in increments of 1
 240                             assert (sv_extra >> 1) == 0, \
 241                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 242                                     (regname, str(extras[extra_idx]))
 243                             # all good: encode as scalar
 244                             sv_extra = sv_extra & 0b01
 245                         else:
 246                             # range is r0-r127 in increments of 4
 247                             assert sv_extra & 0b01 == 0, \
 248                                 "vector field %s cannot fit into EXTRA2 %s" % \
 249                                     (regname, str(extras[extra_idx]))
 250                             # all good: encode as vector (bit 2 set)
 251                             sv_extra = 0b10 | (sv_extra >> 1)
 252                     elif regmode == 'vector':
 253                         # EXTRA3 vector bit needs marking
 254                         sv_extra |= 0b100
 255
 256                 # encode SV-CR 3-bit field into extra, v3.0field
 257                 elif regtype == 'CR_3bit':
 258                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 259                     # now sanity-check (and shrink afterwards)
 260                     if etype == 'EXTRA2':
 261                         if regmode == 'scalar':
 262                             # range is CR0-CR15 in increments of 1
 263                             assert (sv_extra >> 1) == 0, \
 264                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 265                                     (regname, str(extras[extra_idx]))
 266                             # all good: encode as scalar
 267                             sv_extra = sv_extra & 0b01
 268                         else:
 269                             # range is CR0-CR127 in increments of 16
 270                             assert sv_extra & 0b111 == 0, \
 271                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 272                                     (regname, str(extras[extra_idx]))
 273                             # all good: encode as vector (bit 2 set)
 274                             sv_extra = 0b10 | (sv_extra >> 3)
 275                     else:
 276                         if regmode == 'scalar':
 277                             # range is CR0-CR31 in increments of 1
 278                             assert (sv_extra >> 2) == 0, \
 279                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 280                                     (regname, str(extras[extra_idx]))
 281                             # all good: encode as scalar
 282                             sv_extra = sv_extra & 0b11
 283                         else:
 284                             # range is CR0-CR127 in increments of 8
 285                             assert sv_extra & 0b11 == 0, \
 286                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 287                                     (regname, str(extras[extra_idx]))
 288                             # all good: encode as vector (bit 3 set)
 289                             sv_extra = 0b100 | (sv_extra >> 2)
 290
 291                 # encode SV-CR 5-bit field into extra, v3.0field
 292                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 293                 # passed through
 294                 elif regtype == 'CR_5bit':
 295                     cr_subfield = field & 0b11
 296                     field = field >> 2 # strip bottom 2 bits
 297                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 298                     # now sanity-check (and shrink afterwards)
 299                     if etype == 'EXTRA2':
 300                         if regmode == 'scalar':
 301                             # range is CR0-CR15 in increments of 1
 302                             assert (sv_extra >> 1) == 0, \
 303                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 304                                     (regname, str(extras[extra_idx]))
 305                             # all good: encode as scalar
 306                             sv_extra = sv_extra & 0b01
 307                         else:
 308                             # range is CR0-CR127 in increments of 16
 309                             assert sv_extra & 0b111 == 0, \
 310                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 311                                     (regname, str(extras[extra_idx]))
 312                             # all good: encode as vector (bit 2 set)
 313                             sv_extra = 0b10 | (sv_extra >> 3)
 314                     else:
 315                         if regmode == 'scalar':
 316                             # range is CR0-CR31 in increments of 1
 317                             assert (sv_extra >> 2) == 0, \
 318                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 319                                     (regname, str(extras[extra_idx]))
 320                             # all good: encode as scalar
 321                             sv_extra = sv_extra & 0b11
 322                         else:
 323                             # range is CR0-CR127 in increments of 8
 324                             assert sv_extra & 0b11 == 0, \
 325                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 326                                     (regname, str(extras[extra_idx]))
 327                             # all good: encode as vector (bit 3 set)
 328                             sv_extra = 0b100 | (sv_extra >> 2)
 329
 330                     # reconstruct the actual 5-bit CR field
 331                     field = (field << 2) | cr_subfield
 332
 333                 # capture the extra field info
 334                 print ("=>", "%5s" % bin(sv_extra), field)
 335                 extras[extra_idx] = sv_extra
 336
 337                 # append altered field value to v3.0b
 338                 v30b_newfields.append(str(field))
 339
 340             print ("new v3.0B fields", v30b_op, v30b_newfields)
 341             print ("extras", extras)
 342
 343             # rright.  now we have all the info. start creating SVP64 RM
 344             svp64_rm = SVP64RMFields()
 345
 346             # begin with EXTRA fields
 347             for idx, sv_extra in extras.items():
 348                 if idx is None: continue
 349                 if etype == 'EXTRA2':
 350                     svp64_rm.extra2[idx].eq(
 351                         SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 352                 else:
 353                     svp64_rm.extra3[idx].eq(
 354                         SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 355
 356             # parts of svp64_rm
 357             mmode = 0  # bit 0
 358             pmask = 0  # bits 1-3
 359             destwid = 0 # bits 4-5
 360             srcwid = 0 # bits 6-7
 361             subvl = 0   # bits 8-9
 362             smask = 0 # bits 16-18 but only for twin-predication
 363             mode = 0 # bits 19-23
 364
 365             has_pmask = False
 366             has_smask = False
 367
 368             saturation = None
 369             src_zero = 0
 370             dst_zero = 0
 371             sv_mode = None
 372
 373             mapreduce = False
 374             mapreduce_crm = False
 375             mapreduce_svm = False
 376
 377             predresult = False
 378             failfirst = False
 379
 380             # ok let's start identifying opcode augmentation fields
 381             for encmode in opmodes:
 382                 # predicate mask (dest)
 383                 if encmode.startswith("m="):
 384                     pme = encmode
 385                     pmmode, pmask = decode_predicate(encmode[2:])
 386                     mmode = pmmode
 387                     has_pmask = True
 388                 # predicate mask (src, twin-pred)
 389                 elif encmode.startswith("sm="):
 390                     sme = encmode
 391                     smmode, smask = decode_predicate(encmode[3:])
 392                     mmode = smmode
 393                     has_smask = True
 394                 # vec2/3/4
 395                 elif encmode.startswith("vec"):
 396                     subvl = decode_subvl(encmode[3:])
 397                 # elwidth
 398                 elif encmode.startswith("ew="):
 399                     destwid = decode_elwidth(encmode[3:])
 400                 elif encmode.startswith("sw="):
 401                     srcwid = decode_elwidth(encmode[3:])
 402                 # saturation
 403                 elif encmode == 'sats':
 404                     assert sv_mode is None
 405                     saturation = 1
 406                     sv_mode = 0b10
 407                 elif encmode == 'satu':
 408                     assert sv_mode is None
 409                     sv_mode = 0b10
 410                     saturation = 0
 411                 # predicate zeroing
 412                 elif encmode == 'sz':
 413                     src_zero = 1
 414                 elif encmode == 'dz':
 415                     dst_zero = 1
 416                 # failfirst
 417                 elif encmode.startswith("ff="):
 418                     assert sv_mode is None
 419                     sv_mode = 0b01
 420                     failfirst = decode_ffirst(encmode[3:])
 421                 # predicate-result, interestingly same as fail-first
 422                 elif encmode.startswith("pr="):
 423                     assert sv_mode is None
 424                     sv_mode = 0b11
 425                     predresult = decode_ffirst(encmode[3:])
 426                 # map-reduce mode
 427                 elif encmode == 'mr':
 428                     assert sv_mode is None
 429                     sv_mode = 0b00
 430                     mapreduce = True
 431                 elif encmode == 'crm': # CR on map-reduce
 432                     assert sv_mode is None
 433                     sv_mode = 0b00
 434                     mapreduce_crm = True
 435                 elif encmode == 'svm': # sub-vector mode
 436                     mapreduce_svm = True
 437
 438             # sanity-check that 2Pred mask is same mode
 439             if has_pmask and has_smask:
 440                 assert smmode == pmmode, \
 441                     "predicate masks %s and %s must be same reg type" % \
 442                         (pme, sme)
 443
 444             # sanity-check that twin-predication mask only specified in 2P mode
 445             if ptype == '1P':
 446                 assert has_smask == False, \
 447                     "source-mask can only be specified on Twin-predicate ops"
 448
 449             # construct the mode field, doing sanity-checking along the way
 450
 451             if mapreduce_svm:
 452                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 453                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 454
 455             if src_zero:
 456                 assert has_smask, "src zeroing requires a source predicate"
 457             if dst_zero:
 458                 assert has_pmask, "dest zeroing requires a dest predicate"
 459
 460             # "normal" mode
 461             if sv_mode is None:
 462                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 463                 sv_mode = 0b00
 464
 465             # "mapreduce" modes
 466             elif sv_mode == 0b00:
 467                 mode |= (0b1<<2) # sets mapreduce
 468                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
 469                 if mapreduce_crm:
 470                     mode |= (0b1<<4) # sets CRM mode
 471                     assert rc_mode, "CRM only allowed when Rc=1"
 472                 # bit of weird encoding to jam zero-pred or SVM mode in.
 473                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
 474                 if subvl == 0:
 475                     mode |= (src_zero << 3) # predicate src-zeroing
 476                 elif mapreduce_svm:
 477                     mode |= (1 << 3) # SVM mode
 478
 479             # "failfirst" modes
 480             elif sv_mode == 0b01:
 481                 assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
 482                 if failfirst == 'RC1':
 483                     mode |= (0b1<<4) # sets RC1 mode
 484                     mode |= (src_zero << 3) # predicate src-zeroing
 485                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 486                 elif failfirst == '~RC1':
 487                     mode |= (0b1<<4) # sets RC1 mode...
 488                     mode |= (src_zero << 3) # predicate src-zeroing
 489                     mode |= (0b1<<2) # ... with inversion
 490                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 491                 else:
 492                     assert src_zero == 0, "src-zero not allowed in ffirst BO"
 493                     assert rc_mode, "ffirst BO only possible when Rc=1"
 494                     mode |= (failfirst << 2) # set BO
 495
 496             # "saturation" modes
 497             elif sv_mode == 0b10:
 498                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 499                 mode |= (saturation<<2) # sets signed/unsigned saturation
 500
 501             # "predicate-result" modes.  err... code-duplication from ffirst
 502             elif sv_mode == 0b11:
 503                 assert dst_zero == 0, "dest-zero not allowed in predresult mode"
 504                 if predresult == 'RC1':
 505                     mode |= (0b1<<4) # sets RC1 mode
 506                     mode |= (src_zero << 3) # predicate src-zeroing
 507                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 508                 elif predresult == '~RC1':
 509                     mode |= (0b1<<4) # sets RC1 mode...
 510                     mode |= (src_zero << 3) # predicate src-zeroing
 511                     mode |= (0b1<<2) # ... with inversion
 512                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 513                 else:
 514                     assert src_zero == 0, "src-zero not allowed in pr-mode BO"
 515                     assert rc_mode, "pr-mode BO only possible when Rc=1"
 516                     mode |= (predresult << 2) # set BO
 517
 518             # whewww.... modes all done :)
 519             # now put into svp64_rm
 520             mode |= sv_mode
 521             # mode: bits 19-23
 522             svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
 523
 524             # put in predicate masks into svp64_rm
 525             if ptype == '2P':
 526                 # source pred: bits 16-18
 527                 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
 528             # mask mode: bit 0
 529             svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
 530             # 1-pred: bits 1-3
 531             svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
 532
 533             # and subvl: bits 8-9
 534             svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
 535
 536             # put in elwidths
 537             # srcwid: bits 6-7
 538             svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
 539             # destwid: bits 4-5
 540             svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
 541
 542             # nice debug printout. (and now for something completely different)
 543             # https://youtu.be/u0WOIwlXE9g?t=146
 544             svp64_rm_value = svp64_rm.spr.value
 545             print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
 546             print ("    mmode  0    :", bin(mmode))
 547             print ("    pmask  1-3  :", bin(pmask))
 548             print ("    dstwid 4-5  :", bin(destwid))
 549             print ("    srcwid 6-7  :", bin(srcwid))
 550             print ("    subvl  8-9  :", bin(subvl))
 551             print ("    mode   19-23:", bin(mode))
 552             offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 553             for idx, sv_extra in extras.items():
 554                 if idx is None: continue
 555                 start = (10+idx*offs)
 556                 end = start + offs-1
 557                 print ("    extra%d %2d-%2d:" % (idx, start, end),
 558                         bin(sv_extra))
 559             if ptype == '2P':
 560                 print ("    smask  16-17:", bin(smask))
 561             print ()
 562
 563             # first, construct the prefix from its subfields
 564             svp64_prefix = SVP64PrefixFields()
 565             svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
 566             svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
 567             svp64_prefix.rm.eq(svp64_rm.spr)
 568
 569             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
 570             rc = '.' if rc_mode else ''
 571             yield ".long 0x%x" % svp64_prefix.insn.value
 572             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
 573             print ("new v3.0B fields", v30b_op, v30b_newfields)
 574
 575 if __name__ == '__main__':
 576     isa = SVP64Asm(['slw 3, 1, 4',
 577                  'extsw 5, 3',
 578                  'sv.extsw 5, 3',
 579                  'sv.cmpi 5, 1, 3, 2',
 580                  'sv.setb 5, 31',
 581                  'sv.isel 64.v, 3, 2, 65.v',
 582                  'sv.setb/m=r3/sm=1<<r3 5, 31',
 583                  'sv.setb/vec2 5, 31',
 584                  'sv.setb/sw=8/ew=16 5, 31',
 585                  'sv.extsw./ff=eq 5, 31',
 586                  'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
 587                  'sv.extsw./pr=eq 5.v, 31',
 588                  'sv.add. 5.v, 2.v, 1.v',
 589                 ])
 590     print ("list", list(isa))
 591     csvs = SVP64RM()