1 from nmigen
.compat
.sim
import run_simulation
3 from soc
.TLB
.PteEntry
import PteEntry
5 from soc
.TestUtil
.test_helper
import assert_op
13 def check_dirty(dut
, d
, op
):
15 assert_op("Dirty", out_d
, d
, op
)
18 def check_accessed(dut
, a
, op
):
20 assert_op("Accessed", out_a
, a
, op
)
23 def check_global(dut
, o
, op
):
25 assert_op("Global", out
, o
, op
)
28 def check_user(dut
, o
, op
):
30 assert_op("User Mode", out
, o
, op
)
33 def check_xwr(dut
, o
, op
):
35 assert_op("XWR", out
, o
, op
)
38 def check_asid(dut
, o
, op
):
40 assert_op("ASID", out
, o
, op
)
43 def check_pte(dut
, o
, op
):
45 assert_op("ASID", out
, o
, op
)
48 def check_valid(dut
, v
, op
):
50 assert_op("Valid", out_v
, v
, op
)
53 def check_all(dut
, d
, a
, g
, u
, xwr
, v
, asid
, pte
):
54 yield from check_dirty(dut
, d
, 0)
55 yield from check_accessed(dut
, a
, 0)
56 yield from check_global(dut
, g
, 0)
57 yield from check_user(dut
, u
, 0)
58 yield from check_xwr(dut
, xwr
, 0)
59 yield from check_asid(dut
, asid
, 0)
60 yield from check_pte(dut
, pte
, 0)
61 yield from check_valid(dut
, v
, 0)
65 # 80 bits represented. Ignore the MSB as it will be truncated
66 # ASID is bits first 4 hex values (bits 64 - 78)
68 i
= 0x7FFF0000000000000031
76 pte
= 0x0000000000000031
77 yield from set_entry(dut
, i
)
78 yield from check_all(dut
, dirty
, access
, glob
, user
, xwr
, valid
, asid
, pte
)
80 i
= 0x0FFF00000000000000FF
88 pte
= 0x00000000000000FF
89 yield from set_entry(dut
, i
)
90 yield from check_all(dut
, dirty
, access
, glob
, user
, xwr
, valid
, asid
, pte
)
92 i
= 0x0721000000001100001F
100 pte
= 0x000000001100001F
101 yield from set_entry(dut
, i
)
102 yield from check_all(dut
, dirty
, access
, glob
, user
, xwr
, valid
, asid
, pte
)
108 dut
= PteEntry(15, 64)
109 run_simulation(dut
, tbench(dut
), vcd_name
="Waveforms/test_pte_entry.vcd")
110 print("PteEntry Unit Test Success")
113 if __name__
== "__main__":