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add litex wishbone interconnect to 4x 4k SRAMs
[soc.git]
/
Makefile
diff --git
a/Makefile
b/Makefile
index cd8c001dce74d25484ef460619d40e756170f96b..453d0a472441cd6b8845faa64528ab4fda4db7a0 100644
(file)
--- a/
Makefile
+++ b/
Makefile
@@
-29,6
+29,12
@@
testgpio_run_sim:
python3 src/soc/litex/florent/sim.py --cpu=libresoc \
--variant=standardjtagtestgpio
python3 src/soc/litex/florent/sim.py --cpu=libresoc \
--variant=standardjtagtestgpio
+ls180_verilog:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --enable-pll \
+ --enable-xics --enable-sram4x4kblock
+ src/soc/litex/florent/libresoc/libresoc.v
+
test: install
python3 setup.py test # could just run nosetest3...
test: install
python3 setup.py test # could just run nosetest3...