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[soc.git]
/
Makefile
diff --git
a/Makefile
b/Makefile
index abb446dd00b02008e36f3412235f37be5194d312..3d4ea62db5a779f896d1f59665014783681f0523 100644
(file)
--- a/
Makefile
+++ b/
Makefile
@@
-11,13
+11,15
@@
mkpinmux:
cp pinmux/ls180/ls180_pins.py src/soc/debug
cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
cp pinmux/ls180/ls180_pins.py src/soc/debug
cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
-install: gitupdate develop mkpinmux
svanalysis
+install: gitupdate develop mkpinmux
+# this is now actually part of openpower-isa repository
pywriter:
pywriter:
- python3 src/soc/decoder/pseudo/pywriter.py
+ echo "pywriter is part of openpower-isa, run that instead"
+# this is now actually part of openpower-isa repository
svanalysis:
svanalysis:
- python3 libreriscv/openpower/sv_analysis.py
+ echo "sv_analysis is part of openpower-isa, run that instead"
develop:
python3 setup.py develop # yes, develop, not install
develop:
python3 setup.py develop # yes, develop, not install
@@
-36,6
+38,12
@@
testgpio_run_sim:
python3 src/soc/litex/florent/sim.py --cpu=libresoc \
--variant=standardjtagtestgpio
python3 src/soc/litex/florent/sim.py --cpu=libresoc \
--variant=standardjtagtestgpio
+ls180_verilog_nopll:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --disable-pll \
+ --enable-xics --disable-svp64 \
+ src/soc/litex/florent/libresoc/libresoc.v
+
ls180_verilog:
python3 src/soc/simple/issuer_verilog.py \
--debug=jtag --enable-core --enable-pll \
ls180_verilog:
python3 src/soc/simple/issuer_verilog.py \
--debug=jtag --enable-core --enable-pll \
@@
-60,6
+68,9
@@
ls180_4ksram_verilog_build: ls180_4k_verilog
test: install
python3 setup.py test # could just run nosetest3...
test: install
python3 setup.py test # could just run nosetest3...
+pypiupload:
+ $(PYTHON3) setup.py sdist upload
+
# Minimal makefile for Sphinx documentation
#
# Minimal makefile for Sphinx documentation
#