- python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/\
- libresoc.v --enable-testgpio
- python3 src/soc/litex/florent/sim.py --cpu=libresoc --variant=standardjtagtestgpio
+ python3 src/soc/simple/issuer_verilog.py \
+ src/soc/litex/florent/libresoc/libresoc.v \
+ --enable-testgpio
+ python3 src/soc/litex/florent/sim.py --cpu=libresoc \
+ --variant=standardjtagtestgpio
+
+ls180_verilog:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --enable-pll \
+ --enable-xics --enable-sram4x4kblock
+ src/soc/litex/florent/libresoc/libresoc.v