+ python3 src/soc/simple/issuer_verilog.py \
+ src/soc/litex/florent/libresoc/libresoc.v \
+ --enable-testgpio
+ python3 src/soc/litex/florent/sim.py --cpu=libresoc \
+ --variant=standardjtagtestgpio
+
+ls180_verilog_nopll:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --disable-pll \
+ --enable-xics --disable-svp64 \
+ src/soc/litex/florent/libresoc/libresoc.v
+
+ls180_verilog:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --enable-pll \
+ --enable-xics --disable-svp64 \
+ src/soc/litex/florent/libresoc/libresoc.v
+
+ls180_4k_verilog:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --enable-pll \
+ --enable-xics --enable-sram4x4kblock --disable-svp64 \
+ src/soc/litex/florent/libresoc/libresoc.v
+
+# build microwatt "external core", note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+ external_core_top.v
+
+# build the litex libresoc SoC without 4k SRAMs
+ls180_verilog_build: ls180_verilog
+ make -C soc/soc/litex/florent ls180
+
+# build the litex libresoc SoC with 4k SRAMs
+ls180_4ksram_verilog_build: ls180_4k_verilog
+ make -C soc/soc/litex/florent ls1804k