split out putz to separate module

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index f828a67ae0142d16884d34552ce7b9e87c031c65..10b111afe4b6bfa150e880924890066e68fa055c 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -24,6 +24,7 @@ from fpcommon.roundz import (FPRoundData, FPRoundMod, FPRound)
 from fpcommon.corrections import (FPCorrectionsMod, FPCorrections)
 from fpcommon.pack import (FPPackData, FPPackMod, FPPack)
 from fpcommon.normtopack import FPNormToPack
 from fpcommon.corrections import (FPCorrectionsMod, FPCorrections)
 from fpcommon.pack import (FPPackData, FPPackMod, FPPack)
 from fpcommon.normtopack import FPNormToPack

+from fpcommon.putz import (FPPutZ, FPPutZIdx)

 
 
 class FPAddSpecialCasesMod:
 
 
 class FPAddSpecialCasesMod:


@@ -639,57 +640,6 @@ class FPAddStage1(FPState):
 
 
 
 
 
 

-class FPPutZ(FPState):
-
-    def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
-        FPState.__init__(self, state)
-        if to_state is None:
-            to_state = "get_ops"
-        self.to_state = to_state
-        self.in_z = in_z
-        self.out_z = out_z
-        self.in_mid = in_mid
-        self.out_mid = out_mid
-
-    def action(self, m):
-        if self.in_mid is not None:
-            m.d.sync += self.out_mid.eq(self.in_mid)
-        m.d.sync += [
-          self.out_z.z.v.eq(self.in_z)
-        ]
-        with m.If(self.out_z.z.stb & self.out_z.z.ack):
-            m.d.sync += self.out_z.z.stb.eq(0)
-            m.next = self.to_state
-        with m.Else():
-            m.d.sync += self.out_z.z.stb.eq(1)
-
-
-class FPPutZIdx(FPState):
-
-    def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
-        FPState.__init__(self, state)
-        if to_state is None:
-            to_state = "get_ops"
-        self.to_state = to_state
-        self.in_z = in_z
-        self.out_zs = out_zs
-        self.in_mid = in_mid
-
-    def action(self, m):
-        outz_stb = Signal(reset_less=True)
-        outz_ack = Signal(reset_less=True)
-        m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
-                     outz_ack.eq(self.out_zs[self.in_mid].ack),
-                    ]
-        m.d.sync += [
-          self.out_zs[self.in_mid].v.eq(self.in_z.v)
-        ]
-        with m.If(outz_stb & outz_ack):
-            m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
-            m.next = self.to_state
-        with m.Else():
-            m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
-

 
 class FPOpData:
     def __init__(self, width, id_wid):
 
 class FPOpData:
     def __init__(self, width, id_wid):