+class FPAddStage0(FPState, FPID):
+ """ First stage of add. covers same-sign (add) and subtract
+ special-casing when mantissas are greater or equal, to
+ give greatest accuracy.
+ """
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "add_0")
+ FPID.__init__(self, id_wid)
+ self.mod = FPAddStage0Mod(width)
+ self.o = self.mod.ospec()
+
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_a, in_b)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ # NOTE: these could be done as combinatorial (merge add0+add1)
+ m.d.sync += self.o.eq(self.mod.o)
+ m.next = "add_1"
+
+
+class FPAddStage1Data:
+
+ def __init__(self, width):
+ self.z = FPNumBase(width, False)
+ self.of = Overflow()
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.of.eq(i.of)]
+
+
+
+class FPAddStage1Mod(FPState):
+ """ Second stage of add: preparation for normalisation.
+ detects when tot sum is too big (tot[27] is kinda a carry bit)
+ """
+
+ def __init__(self, width):
+ self.width = width
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return FPAddStage0Data(self.width)
+
+ def ospec(self):
+ return FPAddStage1Data(self.width)
+
+ def setup(self, m, in_tot, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add1 = self
+ m.submodules.add1_out_overflow = self.o.of
+
+ m.d.comb += self.i.z.eq(in_z)
+ m.d.comb += self.i.tot.eq(in_tot)
+
+ def elaborate(self, platform):
+ m = Module()
+ #m.submodules.norm1_in_overflow = self.in_of
+ #m.submodules.norm1_out_overflow = self.out_of
+ #m.submodules.norm1_in_z = self.in_z
+ #m.submodules.norm1_out_z = self.out_z
+ m.d.comb += self.o.z.eq(self.i.z)
+ # tot[-1] (MSB) gets set when the sum overflows. shift result down
+ with m.If(self.i.tot[-1]):
+ m.d.comb += [
+ self.o.z.m.eq(self.i.tot[4:]),
+ self.o.of.m0.eq(self.i.tot[4]),
+ self.o.of.guard.eq(self.i.tot[3]),
+ self.o.of.round_bit.eq(self.i.tot[2]),
+ self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
+ self.o.z.e.eq(self.i.z.e + 1)
+ ]
+ # tot[-1] (MSB) zero case
+ with m.Else():
+ m.d.comb += [
+ self.o.z.m.eq(self.i.tot[3:]),
+ self.o.of.m0.eq(self.i.tot[3]),
+ self.o.of.guard.eq(self.i.tot[2]),
+ self.o.of.round_bit.eq(self.i.tot[1]),
+ self.o.of.sticky.eq(self.i.tot[0])
+ ]
+ return m
+
+
+class FPAddStage1(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "add_1")
+ FPID.__init__(self, id_wid)
+ self.mod = FPAddStage1Mod(width)
+ self.out_z = FPNumBase(width, False)
+ self.out_of = Overflow()
+ self.norm_stb = Signal()
+
+ def setup(self, m, in_tot, in_z, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_tot, in_z)
+
+ m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_of.eq(self.mod.out_of)
+ m.d.sync += self.out_z.eq(self.mod.out_z)
+ m.d.sync += self.norm_stb.eq(1)
+ m.next = "normalise_1"
+
+
+class FPNormaliseModSingle:
+
+ def __init__(self, width):
+ self.width = width
+ self.in_z = FPNumBase(width, False)
+ self.out_z = FPNumBase(width, False)
+
+ def setup(self, m, in_z, out_z, modname):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise = self
+ m.d.comb += self.in_z.eq(in_z)
+ m.d.comb += out_z.eq(self.out_z)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ mwid = self.out_z.m_width+2
+ pe = PriorityEncoder(mwid)
+ m.submodules.norm_pe = pe
+
+ m.submodules.norm1_out_z = self.out_z
+ m.submodules.norm1_in_z = self.in_z
+
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
+
+ espec = (len(in_z.e), True)
+ ediff_n126 = Signal(espec, reset_less=True)
+ msr = MultiShiftRMerge(mwid, espec)
+ m.submodules.multishift_r = msr
+
+ m.d.comb += in_z.eq(self.in_z)
+ m.d.comb += in_of.eq(self.in_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.eq(in_z)
+ m.d.comb += self.out_of.eq(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero)
+ # decrease exponent
+ with m.If(decrease):
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(in_z.e), True), reset_less=True)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(pe.o), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
+ self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
+ ]
+
+ return m
+
+
+class FPNorm1ModSingle:
+
+ def __init__(self, width):
+ self.width = width
+ self.out_norm = Signal(reset_less=True)
+ self.in_z = FPNumBase(width, False)
+ self.in_of = Overflow()
+ self.out_z = FPNumBase(width, False)
+ self.out_of = Overflow()
+
+ def setup(self, m, in_z, in_of, out_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise_1 = self
+
+ m.d.comb += self.in_z.eq(in_z)
+ m.d.comb += self.in_of.eq(in_of)
+
+ m.d.comb += out_z.eq(self.out_z)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ mwid = self.out_z.m_width+2
+ pe = PriorityEncoder(mwid)
+ m.submodules.norm_pe = pe
+
+ m.submodules.norm1_out_z = self.out_z
+ m.submodules.norm1_out_overflow = self.out_of
+ m.submodules.norm1_in_z = self.in_z
+ m.submodules.norm1_in_overflow = self.in_of
+
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
+
+ espec = (len(in_z.e), True)
+ ediff_n126 = Signal(espec, reset_less=True)
+ msr = MultiShiftRMerge(mwid, espec)
+ m.submodules.multishift_r = msr
+
+ m.d.comb += in_z.eq(self.in_z)
+ m.d.comb += in_of.eq(self.in_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.eq(in_z)
+ m.d.comb += self.out_of.eq(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ increase = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+ m.d.comb += increase.eq(in_z.exp_lt_n126)
+ # decrease exponent
+ with m.If(decrease):
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(in_z.e), True), reset_less=True)
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
+ in_z.exp_sub_n126)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(limclz), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
+ self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
+ self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[1]), # guard
+ self.out_of.round_bit.eq(temp_s[0]), # round
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ temp_m = Signal(mwid+1, reset_less=True)
+ m.d.comb += [
+ temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
+ in_z.m)),
+ ediff_n126.eq(in_z.N126 - in_z.e),
+ # connect multi-shifter to inp/out mantissa (and ediff)
+ msr.inp.eq(temp_m),
+ msr.diff.eq(ediff_n126),
+ self.out_z.m.eq(msr.m[3:]),
+ self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[2]), # guard
+ self.out_of.round_bit.eq(temp_s[1]), # round
+ self.out_of.sticky.eq(temp_s[0]), # sticky
+ self.out_z.e.eq(in_z.e + ediff_n126),
+ ]
+
+ return m
+
+
+class FPNorm1ModMulti:
+
+ def __init__(self, width, single_cycle=True):
+ self.width = width
+ self.in_select = Signal(reset_less=True)
+ self.in_z = FPNumBase(width, False)
+ self.in_of = Overflow()
+ self.temp_z = FPNumBase(width, False)
+ self.temp_of = Overflow()
+ self.out_z = FPNumBase(width, False)
+ self.out_of = Overflow()
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.submodules.norm1_out_z = self.out_z
+ m.submodules.norm1_out_overflow = self.out_of
+ m.submodules.norm1_temp_z = self.temp_z
+ m.submodules.norm1_temp_of = self.temp_of
+ m.submodules.norm1_in_z = self.in_z
+ m.submodules.norm1_in_overflow = self.in_of
+
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
+
+ # select which of temp or in z/of to use
+ with m.If(self.in_select):
+ m.d.comb += in_z.eq(self.in_z)
+ m.d.comb += in_of.eq(self.in_of)
+ with m.Else():
+ m.d.comb += in_z.eq(self.temp_z)
+ m.d.comb += in_of.eq(self.temp_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.eq(in_z)
+ m.d.comb += self.out_of.eq(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ increase = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+ m.d.comb += increase.eq(in_z.exp_lt_n126)
+ m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
+ # decrease exponent
+ with m.If(decrease):
+ m.d.comb += [
+ self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
+ self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
+ self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
+ self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
+ self.out_of.round_bit.eq(0), # reset round bit
+ self.out_of.m0.eq(in_of.guard),
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ m.d.comb += [
+ self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
+ self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
+ self.out_of.guard.eq(in_z.m[0]),
+ self.out_of.m0.eq(in_z.m[1]),
+ self.out_of.round_bit.eq(in_of.guard),
+ self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
+ ]
+
+ return m
+
+
+class FPNorm1Single(FPState, FPID):
+
+ def __init__(self, width, id_wid, single_cycle=True):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.mod = FPNorm1ModSingle(width)
+ self.out_norm = Signal(reset_less=True)
+ self.out_z = FPNumBase(width)
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z, in_of, self.out_z)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+ m.next = "round"
+
+
+class FPNorm1Multi(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.mod = FPNorm1ModMulti(width)
+ self.stb = Signal(reset_less=True)
+ self.ack = Signal(reset=0, reset_less=True)
+ self.out_norm = Signal(reset_less=True)
+ self.in_accept = Signal(reset_less=True)
+ self.temp_z = FPNumBase(width)
+ self.temp_of = Overflow()
+ self.out_z = FPNumBase(width)
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, norm_stb, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z, in_of, norm_stb,
+ self.in_accept, self.temp_z, self.temp_of,
+ self.out_z, self.out_norm)
+
+ m.d.comb += self.stb.eq(norm_stb)
+ m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
+ m.d.sync += self.temp_of.eq(self.mod.out_of)
+ m.d.sync += self.temp_z.eq(self.out_z)
+ with m.If(self.out_norm):
+ with m.If(self.in_accept):
+ m.d.sync += [
+ self.ack.eq(1),
+ ]
+ with m.Else():
+ m.d.sync += self.ack.eq(0)
+ with m.Else():
+ # normalisation not required (or done).
+ m.next = "round"
+ m.d.sync += self.ack.eq(1)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+
+
+class FPNormToPack(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.width = width
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+
+ # Normalisation (chained to input in_z+in_of)
+ nmod = FPNorm1ModSingle(self.width)
+ n_out_z = FPNumBase(self.width)
+ n_out_roundz = Signal(reset_less=True)
+ nmod.setup(m, in_z, in_of, n_out_z)
+
+ # Rounding (chained to normalisation)
+ rmod = FPRoundMod(self.width)
+ r_out_z = FPNumBase(self.width)
+ rmod.setup(m, n_out_z, n_out_roundz)
+ m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
+ m.d.comb += r_out_z.eq(rmod.out_z)
+
+ # Corrections (chained to rounding)
+ cmod = FPCorrectionsMod(self.width)
+ c_out_z = FPNumBase(self.width)
+ cmod.setup(m, r_out_z)
+ m.d.comb += c_out_z.eq(cmod.out_z)
+
+ # Pack (chained to corrections)
+ self.pmod = FPPackMod(self.width)
+ self.out_z = FPNumBase(self.width)
+ self.pmod.setup(m, c_out_z)
+
+ # Multiplex ID
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m) # copies incoming ID to outgoing
+ m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
+ m.next = "pack_put_z"
+
+
+class FPRoundMod:
+
+ def __init__(self, width):
+ self.in_roundz = Signal(reset_less=True)
+ self.in_z = FPNumBase(width, False)
+ self.out_z = FPNumBase(width, False)
+
+ def setup(self, m, in_z, roundz):
+ m.submodules.roundz = self
+
+ m.d.comb += self.in_z.eq(in_z)
+ m.d.comb += self.in_roundz.eq(roundz)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.d.comb += self.out_z.eq(self.in_z)
+ with m.If(self.in_roundz):
+ m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
+ with m.If(self.in_z.m == self.in_z.m1s): # all 1s
+ m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
+ return m
+
+
+class FPRound(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "round")
+ FPID.__init__(self, id_wid)
+ self.mod = FPRoundMod(width)
+ self.out_z = FPNumBase(width)
+
+ def setup(self, m, in_z, roundz, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z, roundz)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_z.eq(self.mod.out_z)
+ m.next = "corrections"
+
+
+class FPCorrectionsMod:
+
+ def __init__(self, width):
+ self.in_z = FPNumOut(width, False)
+ self.out_z = FPNumOut(width, False)
+
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.corrections = self
+ m.d.comb += self.in_z.eq(in_z)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.corr_in_z = self.in_z
+ m.submodules.corr_out_z = self.out_z
+ m.d.comb += self.out_z.eq(self.in_z)
+ with m.If(self.in_z.is_denormalised):
+ m.d.comb += self.out_z.e.eq(self.in_z.N127)
+ return m
+
+
+class FPCorrections(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "corrections")
+ FPID.__init__(self, id_wid)
+ self.mod = FPCorrectionsMod(width)
+ self.out_z = FPNumBase(width)
+
+ def setup(self, m, in_z, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_z.eq(self.mod.out_z)
+ m.next = "pack"
+
+
+class FPPackMod:
+
+ def __init__(self, width):
+ self.in_z = FPNumOut(width, False)
+ self.out_z = FPNumOut(width, False)
+
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.pack = self
+ m.d.comb += self.in_z.eq(in_z)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.pack_in_z = self.in_z
+ with m.If(self.in_z.is_overflowed):
+ m.d.comb += self.out_z.inf(self.in_z.s)
+ with m.Else():
+ m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
+ return m
+
+
+class FPPack(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "pack")
+ FPID.__init__(self, id_wid)
+ self.mod = FPPackMod(width)
+ self.out_z = FPNumOut(width, False)
+
+ def setup(self, m, in_z, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
+ m.next = "pack_put_z"
+
+
+class FPPutZ(FPState):
+
+ def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
+ FPState.__init__(self, state)
+ if to_state is None:
+ to_state = "get_ops"
+ self.to_state = to_state
+ self.in_z = in_z
+ self.out_z = out_z
+ self.in_mid = in_mid
+ self.out_mid = out_mid
+
+ def action(self, m):
+ if self.in_mid is not None:
+ m.d.sync += self.out_mid.eq(self.in_mid)
+ m.d.sync += [
+ self.out_z.v.eq(self.in_z.v)
+ ]
+ with m.If(self.out_z.stb & self.out_z.ack):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = self.to_state
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
+
+
+class FPPutZIdx(FPState):
+
+ def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
+ FPState.__init__(self, state)
+ if to_state is None:
+ to_state = "get_ops"
+ self.to_state = to_state
+ self.in_z = in_z
+ self.out_zs = out_zs
+ self.in_mid = in_mid
+
+ def action(self, m):
+ outz_stb = Signal(reset_less=True)
+ outz_ack = Signal(reset_less=True)
+ m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
+ outz_ack.eq(self.out_zs[self.in_mid].ack),
+ ]
+ m.d.sync += [
+ self.out_zs[self.in_mid].v.eq(self.in_z.v)
+ ]
+ with m.If(outz_stb & outz_ack):
+ m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
+ m.next = self.to_state
+ with m.Else():
+ m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
+
+
+class FPADDBaseMod(FPID):
+
+ def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
+ """ IEEE754 FP Add
+
+ * width: bit-width of IEEE754. supported: 16, 32, 64
+ * id_wid: an identifier that is sync-connected to the input
+ * single_cycle: True indicates each stage to complete in 1 clock
+ * compact: True indicates a reduced number of stages
+ """
+ FPID.__init__(self, id_wid)