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replace o_ready with ready_o
[ieee754fpu.git]
/
src
/
add
/
test_outmux_pipe.py
diff --git
a/src/add/test_outmux_pipe.py
b/src/add/test_outmux_pipe.py
index 9c9e0cc77f168c1bf52ca93cb15ca1b11e15c5e0..c3db79f77891822c837535b1e3c105f737220fc3 100644
(file)
--- a/
src/add/test_outmux_pipe.py
+++ b/
src/add/test_outmux_pipe.py
@@
-69,10
+69,10
@@
class OutputTest:
yield rs.i_data.data.eq(op2)
yield rs.i_data.mid.eq(mid)
yield
yield rs.i_data.data.eq(op2)
yield rs.i_data.mid.eq(mid)
yield
- o_p_ready = yield rs.
o_ready
+ o_p_ready = yield rs.
ready_o
while not o_p_ready:
yield
while not o_p_ready:
yield
- o_p_ready = yield rs.
o_ready
+ o_p_ready = yield rs.
ready_o
print ("send", mid, i, hex(op2))
print ("send", mid, i, hex(op2))
@@
-139,7
+139,7
@@
class TestSyncToPriorityPipe(Elaboratable):
return m
def ports(self):
return m
def ports(self):
- res = [self.p.i_valid, self.p.
o_ready
] + \
+ res = [self.p.i_valid, self.p.
ready_o
] + \
self.p.i_data.ports()
for i in range(len(self.n)):
res += [self.n[i].i_ready, self.n[i].o_valid] + \
self.p.i_data.ports()
for i in range(len(self.n)):
res += [self.n[i].i_ready, self.n[i].o_valid] + \