- m.d.sync += intfus.int_dest_i.eq(self.int_dest_i)
- m.d.sync += intfus.int_src1_i.eq(self.int_src1_i)
- m.d.sync += intfus.int_src2_i.eq(self.int_src2_i)
+ m.d.comb += intfus.int_dest_i.eq(self.int_dest_i)
+ m.d.comb += intfus.int_src1_i.eq(self.int_src1_i)
+ m.d.comb += intfus.int_src2_i.eq(self.int_src2_i)
fn_issue_o = Signal(n_int_fus, reset_less=True)
for i in range(n_int_fus):
fn_issue_o = Signal(n_int_fus, reset_less=True)
for i in range(n_int_fus):
m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
# XXX sync, so as to stop a simulation infinite loop
m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
# XXX sync, so as to stop a simulation infinite loop
- m.d.sync += intpick1.req_rel_i[0].eq(cu.req_rel_o[0])
- m.d.sync += intpick1.req_rel_i[1].eq(cu.req_rel_o[1])
+ m.d.comb += intpick1.req_rel_i[0].eq(cu.req_rel_o[0])
+ m.d.comb += intpick1.req_rel_i[1].eq(cu.req_rel_o[1])
- m.d.comb += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
- m.d.comb += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
- m.d.comb += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
- m.d.comb += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
+ m.d.sync += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
+ m.d.sync += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
+ m.d.sync += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
+ m.d.sync += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
#---------
# Connect Register File(s)
#---------
print ("intregdeps wen len", len(intregdeps.dest_rsel_o))
#---------
# Connect Register File(s)
#---------
print ("intregdeps wen len", len(intregdeps.dest_rsel_o))
m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
- m.d.comb += cu.go_rd_i[i].eq(go_rd_o[i])
- m.d.comb += cu.go_wr_i[i].eq(go_wr_o[i])
- m.d.comb += cu.issue_i[i].eq(fn_issue_o[i])
+ m.d.sync += cu.go_rd_i[i].eq(go_rd_o[i])
+ m.d.sync += cu.go_wr_i[i].eq(go_wr_o[i])
+ m.d.sync += cu.issue_i[i].eq(fn_issue_o[i])
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
while True:
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
while True: