- n_comb_stages = 3 # TODO (depends on how many RS's we want)
-
- # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
- # then there is guard, round and sticky at the LSB end.
- # also: round up to nearest radix
- if width == 16:
- extra = 5
- elif width == 32:
- extra = 6
- elif width == 64:
- extra = 5
- fmt.m_width = roundup(fmt.m_width + extra, log2_radix)
- print ("width", fmt.m_width)
-
- cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
+
+ # TODO (depends on how many RS's we want)
+ #n_comb_stages = width // (2 * log2_radix) # 2 compute steps per stage
+ n_comb_stages = 2 # FIXME: switch back
+
+ fraction_width = fmt.fraction_width
+
+ # extra bits needed: guard + round
+ fraction_width += 2
+
+ # rounding width to a multiple of log2_radix is not needed,
+ # DivPipeCoreCalculateStage just internally reduces log2_radix on
+ # the last stage
+ cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)