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more random experimenting
[ieee754fpu.git]
/
src
/
ieee754
/
fpdiv
/
pipeline.py
diff --git
a/src/ieee754/fpdiv/pipeline.py
b/src/ieee754/fpdiv/pipeline.py
index c6d6ca10a76cd8d0e1aee11e469e1fbf3e49c563..119db0f57f626438d4100e7a331d13cb125fc6b3 100644
(file)
--- a/
src/ieee754/fpdiv/pipeline.py
+++ b/
src/ieee754/fpdiv/pipeline.py
@@
-159,12
+159,12
@@
class FPDIVMuxInOut(ReservationStations):
fmt = FPFormat.standard(width)
log2_radix = 2
fmt = FPFormat.standard(width)
log2_radix = 2
- # ...
4
extra bits on the mantissa: MSB is zero, MSB-1 is 1
- # then there is guard
and round
at the LSB end.
+ # ...
5
extra bits on the mantissa: MSB is zero, MSB-1 is 1
+ # then there is guard
, round and sticky
at the LSB end.
# also: round up to nearest radix
# also: round up to nearest radix
- fmt.m_width = roundup(fmt.m_width +
4
, log2_radix)
+ fmt.m_width = roundup(fmt.m_width +
5
, log2_radix)
- cfg = DivPipeCoreConfig(fmt.m_width,
0*
fmt.fraction_width, log2_radix)
+ cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
self.pspec.fpformat = fmt
self.pspec.log2_radix = log2_radix
self.pspec.fpformat = fmt
self.pspec.log2_radix = log2_radix