- # get the standard mantissa width, store in the pspec
- # (used in DivPipeBaseStage.get_core_config)
- p = FPFormat.standard(width)
- self.pspec.m_width = p.m_width
+ # get the standard mantissa width, store in the pspec HOWEVER...
+ fmt = FPFormat.standard(width)
+ log2_radix = 2
+
+ # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
+ # then there is guard, round and sticky at the LSB end.
+ # also: round up to nearest radix
+ fmt.m_width = roundup(fmt.m_width + 5, log2_radix)
+ print ("width", fmt.m_width)
+
+ cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
+
+ self.pspec.fpformat = fmt
+ self.pspec.log2_radix = log2_radix
+ self.pspec.core_config = cfg