+def get_term(value, shift=0, enabled=None):
+ if enabled is not None:
+ value = Mux(enabled, value, 0)
+ if shift > 0:
+ value = Cat(Repl(C(0, 1), shift), value)
+ else:
+ assert shift == 0
+ return value
+
+
+class ProductTerm(Elaboratable):
+ """ this class creates a single product term (a[..]*b[..]).
+ it has a design flaw in that is the *output* that is selected,
+ where the multiplication(s) are combinatorially generated
+ all the time.
+ """
+
+ def __init__(self, width, twidth, pbwid, a_index, b_index):
+ self.a_index = a_index
+ self.b_index = b_index
+ shift = 8 * (self.a_index + self.b_index)
+ self.pwidth = width
+ self.twidth = twidth
+ self.width = width*2
+ self.shift = shift
+
+ self.ti = Signal(self.width, reset_less=True)
+ self.term = Signal(twidth, reset_less=True)
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+
+ self.tl = tl = []
+ min_index = min(self.a_index, self.b_index)
+ max_index = max(self.a_index, self.b_index)
+ for i in range(min_index, max_index):
+ tl.append(self.pb_en[i])
+ name = "te_%d_%d" % (self.a_index, self.b_index)
+ if len(tl) > 0:
+ term_enabled = Signal(name=name, reset_less=True)
+ else:
+ term_enabled = None
+ self.enabled = term_enabled
+ self.term.name = "term_%d_%d" % (a_index, b_index) # rename
+
+ def elaborate(self, platform):
+
+ m = Module()
+ if self.enabled is not None:
+ m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
+
+ bsa = Signal(self.width, reset_less=True)
+ bsb = Signal(self.width, reset_less=True)
+ a_index, b_index = self.a_index, self.b_index
+ pwidth = self.pwidth
+ m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
+ m.d.comb += self.ti.eq(bsa * bsb)
+ m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
+ """
+ #TODO: sort out width issues, get inputs a/b switched on/off.
+ #data going into Muxes is 1/2 the required width
+
+ pwidth = self.pwidth
+ width = self.width
+ bsa = Signal(self.twidth//2, reset_less=True)
+ bsb = Signal(self.twidth//2, reset_less=True)
+ asel = Signal(width, reset_less=True)
+ bsel = Signal(width, reset_less=True)
+ a_index, b_index = self.a_index, self.b_index
+ m.d.comb += asel.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsel.eq(self.b.bit_select(b_index * pwidth, pwidth))
+ m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled))
+ m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled))
+ m.d.comb += self.ti.eq(bsa * bsb)
+ m.d.comb += self.term.eq(self.ti)
+ """
+
+ return m
+
+
+class ProductTerms(Elaboratable):
+ """ creates a bank of product terms. also performs the actual bit-selection
+ this class is to be wrapped with a for-loop on the "a" operand.
+ it creates a second-level for-loop on the "b" operand.
+ """
+ def __init__(self, width, twidth, pbwid, a_index, blen):
+ self.a_index = a_index
+ self.blen = blen
+ self.pwidth = width
+ self.twidth = twidth
+ self.pbwid = pbwid
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+ self.terms = [Signal(twidth, name="term%d"%i, reset_less=True) \
+ for i in range(blen)]
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ for b_index in range(self.blen):
+ t = ProductTerm(self.pwidth, self.twidth, self.pbwid,
+ self.a_index, b_index)
+ setattr(m.submodules, "term_%d" % b_index, t)
+
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(self.pb_en)
+
+ m.d.comb += self.terms[b_index].eq(t.term)
+
+ return m
+
+class LSBNegTerm(Elaboratable):
+
+ def __init__(self, bit_width):
+ self.bit_width = bit_width
+ self.part = Signal(reset_less=True)
+ self.signed = Signal(reset_less=True)
+ self.op = Signal(bit_width, reset_less=True)
+ self.msb = Signal(reset_less=True)
+ self.nt = Signal(bit_width*2, reset_less=True)
+ self.nl = Signal(bit_width*2, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+ bit_wid = self.bit_width
+ ext = Repl(0, bit_wid) # extend output to HI part
+
+ # determine sign of each incoming number *in this partition*
+ enabled = Signal(reset_less=True)
+ m.d.comb += enabled.eq(self.part & self.msb & self.signed)
+
+ # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
+ # negation operation is split into a bitwise not and a +1.
+ # likewise for 16, 32, and 64-bit values.
+
+ # width-extended 1s complement if a is signed, otherwise zero
+ comb += self.nt.eq(Mux(enabled, Cat(ext, ~self.op), 0))
+
+ # add 1 if signed, otherwise add zero
+ comb += self.nl.eq(Cat(ext, enabled, Repl(0, bit_wid-1)))
+
+ return m
+
+
+class Part(Elaboratable):
+ """ a key class which, depending on the partitioning, will determine
+ what action to take when parts of the output are signed or unsigned.
+
+ this requires 2 pieces of data *per operand, per partition*:
+ whether the MSB is HI/LO (per partition!), and whether a signed
+ or unsigned operation has been *requested*.
+
+ once that is determined, signed is basically carried out
+ by splitting 2's complement into 1's complement plus one.
+ 1's complement is just a bit-inversion.
+
+ the extra terms - as separate terms - are then thrown at the
+ AddReduce alongside the multiplication part-results.
+ """
+ def __init__(self, width, n_parts, n_levels, pbwid):
+
+ # inputs
+ self.a = Signal(64)
+ self.b = Signal(64)
+ self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
+ self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.pbs = Signal(pbwid, reset_less=True)
+
+ # outputs
+ self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+ self.delayed_parts = [
+ [Signal(name=f"delayed_part_{delay}_{i}")
+ for i in range(n_parts)]
+ for delay in range(n_levels)]
+ # XXX REALLY WEIRD BUG - have to take a copy of the last delayed_parts
+ self.dplast = [Signal(name=f"dplast_{i}")
+ for i in range(n_parts)]
+
+ self.not_a_term = Signal(width)
+ self.neg_lsb_a_term = Signal(width)
+ self.not_b_term = Signal(width)
+ self.neg_lsb_b_term = Signal(width)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ pbs, parts, delayed_parts = self.pbs, self.parts, self.delayed_parts
+ # negated-temporary copy of partition bits
+ npbs = Signal.like(pbs, reset_less=True)
+ m.d.comb += npbs.eq(~pbs)
+ byte_count = 8 // len(parts)
+ for i in range(len(parts)):
+ pbl = []
+ pbl.append(npbs[i * byte_count - 1])
+ for j in range(i * byte_count, (i + 1) * byte_count - 1):
+ pbl.append(pbs[j])
+ pbl.append(npbs[(i + 1) * byte_count - 1])
+ value = Signal(len(pbl), name="value_%di" % i, reset_less=True)
+ m.d.comb += value.eq(Cat(*pbl))
+ m.d.comb += parts[i].eq(~(value).bool())
+ m.d.comb += delayed_parts[0][i].eq(parts[i])
+ m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
+ for j in range(len(delayed_parts)-1)]
+ m.d.comb += self.dplast[i].eq(delayed_parts[-1][i])
+
+ not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
+ self.not_a_term, self.neg_lsb_a_term, \
+ self.not_b_term, self.neg_lsb_b_term
+
+ byte_width = 8 // len(parts) # byte width
+ bit_wid = 8 * byte_width # bit width
+ nat, nbt, nla, nlb = [], [], [], []
+ for i in range(len(parts)):
+ # work out bit-inverted and +1 term for a.
+ pa = LSBNegTerm(bit_wid)
+ setattr(m.submodules, "lnt_%d_a_%d" % (bit_wid, i), pa)
+ m.d.comb += pa.part.eq(parts[i])
+ m.d.comb += pa.op.eq(self.a.bit_select(bit_wid * i, bit_wid))
+ m.d.comb += pa.signed.eq(self.b_signed[i * byte_width]) # yes b
+ m.d.comb += pa.msb.eq(self.b[(i + 1) * bit_wid - 1]) # really, b
+ nat.append(pa.nt)
+ nla.append(pa.nl)
+
+ # work out bit-inverted and +1 term for b
+ pb = LSBNegTerm(bit_wid)
+ setattr(m.submodules, "lnt_%d_b_%d" % (bit_wid, i), pb)
+ m.d.comb += pb.part.eq(parts[i])
+ m.d.comb += pb.op.eq(self.b.bit_select(bit_wid * i, bit_wid))
+ m.d.comb += pb.signed.eq(self.a_signed[i * byte_width]) # yes a
+ m.d.comb += pb.msb.eq(self.a[(i + 1) * bit_wid - 1]) # really, a
+ nbt.append(pb.nt)
+ nlb.append(pb.nl)
+
+ # concatenate together and return all 4 results.
+ m.d.comb += [not_a_term.eq(Cat(*nat)),
+ not_b_term.eq(Cat(*nbt)),
+ neg_lsb_a_term.eq(Cat(*nla)),
+ neg_lsb_b_term.eq(Cat(*nlb)),
+ ]
+
+ return m
+
+
+class IntermediateOut(Elaboratable):
+ """ selects the HI/LO part of the multiplication, for a given bit-width
+ the output is also reconstructed in its SIMD (partition) lanes.
+ """
+ def __init__(self, width, out_wid, n_parts):
+ self.width = width
+ self.n_parts = n_parts
+ self.delayed_part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
+ for i in range(8)]
+ self.intermed = Signal(out_wid, reset_less=True)
+ self.output = Signal(out_wid//2, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ ol = []
+ w = self.width
+ sel = w // 8
+ for i in range(self.n_parts):
+ op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
+ m.d.comb += op.eq(
+ Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
+ self.intermed.bit_select(i * w*2, w),
+ self.intermed.bit_select(i * w*2 + w, w)))
+ ol.append(op)
+ m.d.comb += self.output.eq(Cat(*ol))
+
+ return m
+
+
+class FinalOut(Elaboratable):
+ """ selects the final output based on the partitioning.
+
+ each byte is selectable independently, i.e. it is possible
+ that some partitions requested 8-bit computation whilst others
+ requested 16 or 32 bit.
+ """
+ def __init__(self, out_wid):
+ # inputs
+ self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+
+ self.i8 = Signal(out_wid, reset_less=True)
+ self.i16 = Signal(out_wid, reset_less=True)
+ self.i32 = Signal(out_wid, reset_less=True)
+ self.i64 = Signal(out_wid, reset_less=True)
+
+ # output
+ self.out = Signal(out_wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ ol = []
+ for i in range(8):
+ # select one of the outputs: d8 selects i8, d16 selects i16
+ # d32 selects i32, and the default is i64.
+ # d8 and d16 are ORed together in the first Mux
+ # then the 2nd selects either i8 or i16.
+ # if neither d8 nor d16 are set, d32 selects either i32 or i64.
+ op = Signal(8, reset_less=True, name="op_%d" % i)
+ m.d.comb += op.eq(
+ Mux(self.d8[i] | self.d16[i // 2],
+ Mux(self.d8[i], self.i8.bit_select(i * 8, 8),
+ self.i16.bit_select(i * 8, 8)),
+ Mux(self.d32[i // 4], self.i32.bit_select(i * 8, 8),
+ self.i64.bit_select(i * 8, 8))))
+ ol.append(op)
+ m.d.comb += self.out.eq(Cat(*ol))
+ return m
+
+
+class OrMod(Elaboratable):
+ """ ORs four values together in a hierarchical tree
+ """
+ def __init__(self, wid):
+ self.wid = wid
+ self.orin = [Signal(wid, name="orin%d" % i, reset_less=True)
+ for i in range(4)]
+ self.orout = Signal(wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ or1 = Signal(self.wid, reset_less=True)
+ or2 = Signal(self.wid, reset_less=True)
+ m.d.comb += or1.eq(self.orin[0] | self.orin[1])
+ m.d.comb += or2.eq(self.orin[2] | self.orin[3])
+ m.d.comb += self.orout.eq(or1 | or2)
+
+ return m
+
+
+class Signs(Elaboratable):
+ """ determines whether a or b are signed numbers
+ based on the required operation type (OP_MUL_*)
+ """
+
+ def __init__(self):
+ self.part_ops = Signal(2, reset_less=True)
+ self.a_signed = Signal(reset_less=True)
+ self.b_signed = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ asig = self.part_ops != OP_MUL_UNSIGNED_HIGH
+ bsig = (self.part_ops == OP_MUL_LOW) \
+ | (self.part_ops == OP_MUL_SIGNED_HIGH)
+ m.d.comb += self.a_signed.eq(asig)
+ m.d.comb += self.b_signed.eq(bsig)
+
+ return m
+
+
projects / ieee754fpu.git / blobdiff