+ self.traptype = Signal(TT.size, reset_less=True) # trap main_stage.py
+ self.ldst_exc = LDSTException("exc")
+ self.trapaddr = Signal(13, reset_less=True)
+ self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
+ self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
+ self.is_32bit = Signal(reset_less=True)
+
+
+class Decode2ToOperand(IssuerDecode2ToOperand):
+
+ def __init__(self, name=None):
+
+ IssuerDecode2ToOperand.__init__(self, name=name)
+
+ # instruction, type and decoded information
+ self.imm_data = Data(64, name="imm")
+ self.invert_in = Signal(reset_less=True)
+ self.zero_a = Signal(reset_less=True)