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whoops changed name of ALUInputData to LogicalInputData
[soc.git]
/
src
/
soc
/
decoder
/
power_fieldsn.py
diff --git
a/src/soc/decoder/power_fieldsn.py
b/src/soc/decoder/power_fieldsn.py
index e603bbd3a68dca45e8c42cf1dac80a5b24034a4d..74fcd00733f0175bd36c31f5b9c8097afbf6548a 100644
(file)
--- a/
src/soc/decoder/power_fieldsn.py
+++ b/
src/soc/decoder/power_fieldsn.py
@@
-1,5
+1,5
@@
from collections import OrderedDict
from collections import OrderedDict
-from power_fields import DecodeFields, BitRange
+from
soc.decoder.
power_fields import DecodeFields, BitRange
from nmigen import Module, Elaboratable, Signal, Cat
from nmigen.cli import rtlil
from nmigen import Module, Elaboratable, Signal, Cat
from nmigen.cli import rtlil
@@
-9,14
+9,14
@@
class SignalBitRange(BitRange):
BitRange.__init__(self)
self.signal = signal
BitRange.__init__(self)
self.signal = signal
+ def _rev(self, k):
+ width = self.signal.shape()[0]
+ return width-1-k
+
def __getitem__(self, subs):
# *sigh* field numberings are bit-inverted. PowerISA 3.0B section 1.3.2
def __getitem__(self, subs):
# *sigh* field numberings are bit-inverted. PowerISA 3.0B section 1.3.2
- width = self.signal.shape()[0]
- print (dir(self))
- print (self.items())
if isinstance(subs, slice):
res = []
if isinstance(subs, slice):
res = []
- print (subs)
start, stop, step = subs.start, subs.stop, subs.step
if step is None:
step = 1
start, stop, step = subs.start, subs.stop, subs.step
if step is None:
step = 1
@@
-25,20
+25,21
@@
class SignalBitRange(BitRange):
if stop is None:
stop = -1
if start < 0:
if stop is None:
stop = -1
if start < 0:
- start = len(self)
- start -
1
+ start = len(self)
+ start +
1
if stop < 0:
if stop < 0:
- stop = len(self) - stop - 1
- print ("range", start, stop, step)
+ stop = len(self) + stop + 1
for t in range(start, stop, step):
for t in range(start, stop, step):
+ t = len(self) - 1 - t # invert field back
k = OrderedDict.__getitem__(self, t)
k = OrderedDict.__getitem__(self, t)
- print ("t", t, k)
- res.append(self.signal[width-k-1])
+ res.append(self.signal[self._rev(k)]) # reverse-order here
return Cat(*res)
else:
return Cat(*res)
else:
+ if subs < 0:
+ subs = len(self) + subs
+ subs = len(self) - 1 - subs # invert field back
k = OrderedDict.__getitem__(self, subs)
k = OrderedDict.__getitem__(self, subs)
- return self.signal[
width-k-1]
+ return self.signal[
self._rev(k)] # reverse-order here
- print ("translated", subs, translated)
class SigDecode(Elaboratable):
class SigDecode(Elaboratable):
@@
-47,20
+48,14
@@
class SigDecode(Elaboratable):
self.opcode_in = Signal(width, reset_less=False)
self.df = DecodeFields(SignalBitRange, [self.opcode_in])
self.df.create_specs()
self.opcode_in = Signal(width, reset_less=False)
self.df = DecodeFields(SignalBitRange, [self.opcode_in])
self.df.create_specs()
- self.x_s = Signal(len(self.df.FormX.S), reset_less=True)
- self.x_sh = Signal(len(self.df.FormX.SH), reset_less=True)
- self.dq_xs_s = Signal(len(self.df.FormDQ.SX_S), reset_less=True)
def elaborate(self, platform):
m = Module()
comb = m.d.comb
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- comb += self.x_s.eq(self.df.FormX.S[0])
- comb += self.x_sh.eq(self.df.FormX.SH[0:-1])
- comb += self.dq_xs_s.eq(self.df.FormDQ.SX_S[0:-1])
return m
def ports(self):
return m
def ports(self):
- return [self.opcode_in
, self.x_s, self.x_sh
]
+ return [self.opcode_in]
def create_sigdecode():
s = SigDecode(32)
def create_sigdecode():
s = SigDecode(32)