# to trigger *from* the opcode latch instead.
src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
src_sel = Signal(reset_less=True)
# to trigger *from* the opcode latch instead.
src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
src_sel = Signal(reset_less=True)
m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
# overwrite 1st src-latch with immediate-muxed stuff
sl[i][0] = src_or_imm
m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
# overwrite 1st src-latch with immediate-muxed stuff
sl[i][0] = src_or_imm
m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
# read-done,wr-proceed latch
m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
# read-done,wr-proceed latch
m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done
# wr-done, back-to-start latch
m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done
# wr-done, back-to-start latch
- m.d.comb += rst_l.s.eq(all_rd) # set when read-phase is fully done
- m.d.comb += rst_l.r.eq(rst_r) # *off* on issue
+ m.d.sync += rst_l.s.eq(all_rd) # set when read-phase is fully done
+ m.d.sync += rst_l.r.eq(rst_r) # *off* on issue
# opcode latch (not using go_rd_i) - inverted so that busy resets to 0
m.d.sync += opc_l.s.eq(self.issue_i) # set on issue
# opcode latch (not using go_rd_i) - inverted so that busy resets to 0
m.d.sync += opc_l.s.eq(self.issue_i) # set on issue
m.d.sync += req_l.r.eq(reset_w | prev_wr_go)
# pass operation to the ALU (sync: plenty time to wait for src reads)
m.d.sync += req_l.r.eq(reset_w | prev_wr_go)
# pass operation to the ALU (sync: plenty time to wait for src reads)
else:
data_r = Signal.like(lro, name=name, reset_less=True)
wrok.append(ok & self.busy_o)
else:
data_r = Signal.like(lro, name=name, reset_less=True)
wrok.append(ok & self.busy_o)
- latchregister(m, lro, data_r, alu_pulsem, name + "_l")
+ with m.If(alu_pulse):
+ m.d.sync += data_r.eq(lro)
+ with m.If(self.issue_i):
+ m.d.sync += data_r.eq(0)
if hasattr(op, "imm_data"):
# select immediate if opcode says so. however also change the latch
# to trigger *from* the opcode latch instead.
if hasattr(op, "imm_data"):
# select immediate if opcode says so. however also change the latch
# to trigger *from* the opcode latch instead.
self._mux_op(m, sl, op_is_imm, imm, 1)
# create a latch/register for src1/src2 (even if it is a copy of imm)
self._mux_op(m, sl, op_is_imm, imm, 1)
# create a latch/register for src1/src2 (even if it is a copy of imm)