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get compldst.py unit test up and running after modifications to ALU
[soc.git]
/
src
/
soc
/
experiment
/
compalu_multi.py
diff --git
a/src/soc/experiment/compalu_multi.py
b/src/soc/experiment/compalu_multi.py
index 10a2b4110ee993af50d813da3183cbe6c8783288..dddb1f7730c1b2f3c467683adb22a6e5299412da 100644
(file)
--- a/
src/soc/experiment/compalu_multi.py
+++ b/
src/soc/experiment/compalu_multi.py
@@
-231,9
+231,7
@@
def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
yield
yield dut.issue_i.eq(0)
yield
yield
yield dut.issue_i.eq(0)
yield
- yield dut.go_rd_i.eq(0b10)
- yield
- yield dut.go_rd_i.eq(0b01)
+ yield dut.go_rd_i.eq(0b11)
while True:
yield
rd_rel_o = yield dut.rd_rel_o
while True:
yield
rd_rel_o = yield dut.rd_rel_o
@@
-281,11
+279,12
@@
def test_scoreboard():
alu = ALU(16)
dut = ComputationUnitNoDelay(16, alu)
m.submodules.cu = dut
alu = ALU(16)
dut = ComputationUnitNoDelay(16, alu)
m.submodules.cu = dut
- run_simulation(m, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_compalu.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_compalu.il", "w") as f:
f.write(vl)
+ run_simulation(m, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
+
if __name__ == '__main__':
test_scoreboard()
if __name__ == '__main__':
test_scoreboard()