update old TestMicrowattMemoryPortInterface

[soc.git] / src / soc / experiment / compldst_multi.py

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 41739ed4551fb6c43124bfea7ae6bbcabbf5aa8c..be2c9031759b7b70971aa7bce5e1dab5af1dfa34 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -20,6 +20,11 @@ Loads are activated when Go_Write[0] is enabled.  The EA is computed,
 and (as long as there was no exception) the data comes out (at any
 time from the PortInterface), and is captured by the LDCompSTUnit.
 
 and (as long as there was no exception) the data comes out (at any
 time from the PortInterface), and is captured by the LDCompSTUnit.
 

+TODO: dcbz, yes, that's going to be complicated, has to be done
+ with great care, to detect the case when dcbz is set
+ and *not* expect to read any data, just the address.
+ so, wait for RA but not RB.
+

 Both LD and ST may request that the address be computed from summing
 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
 the immediate (from the opcode).
 Both LD and ST may request that the address be computed from summing
 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
 the immediate (from the opcode).


@@ -53,6 +58,8 @@ the nested FSMs below are *combinatorial*).
 
     * A third FSM activates to cover ST.  it activates if op_is_st is true
 
 
     * A third FSM activates to cover ST.  it activates if op_is_st is true
 

+    * TODO document DCBZ (not complete yet)
+

     * The "overall" (fourth) FSM coordinates the progression and completion
       of the three other FSMs, firing "WR_RESET" which switches off "busy"
 
     * The "overall" (fourth) FSM coordinates the progression and completion
       of the three other FSMs, firing "WR_RESET" which switches off "busy"
 


@@ -89,11 +96,22 @@ from nmutil.extend import exts
 
 from soc.experiment.compalu_multi import go_record, CompUnitRecord
 from soc.experiment.l0_cache import PortInterface
 
 from soc.experiment.compalu_multi import go_record, CompUnitRecord
 from soc.experiment.l0_cache import PortInterface

+from soc.experiment.pimem import LDSTException

 from soc.fu.regspec import RegSpecAPI
 
 from soc.fu.regspec import RegSpecAPI
 

-from soc.decoder.power_enums import MicrOp, Function, LDSTMode
+from openpower.decoder.power_enums import MicrOp, Function, LDSTMode

 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset

-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
+from openpower.consts import MSR
+from soc.config.test.test_loadstore import TestMemPspec
+
+# for debugging dcbz
+from nmutil.util import Display
+
+
+# TODO: LDSTInputData and LDSTOutputData really should be used
+# here, to make things more like the other CompUnits.  currently,
+# also, RegSpecAPI is used explicitly here

 
 
 class LDSTCompUnitRecord(CompUnitRecord):
 
 
 class LDSTCompUnitRecord(CompUnitRecord):


@@ -104,7 +122,7 @@ class LDSTCompUnitRecord(CompUnitRecord):
         self.ad = go_record(1, name="cu_ad")  # address go in, req out
         self.st = go_record(1, name="cu_st")  # store go in, req out
 
         self.ad = go_record(1, name="cu_ad")  # address go in, req out
         self.st = go_record(1, name="cu_st")  # store go in, req out
 

-        self.addr_exc_o = Signal(reset_less=True)   # address exception
+        self.exc_o = LDSTException("exc_o")

 
         self.ld_o = Signal(reset_less=True)  # operation is a LD
         self.st_o = Signal(reset_less=True)  # operation is a ST
 
         self.ld_o = Signal(reset_less=True)  # operation is a LD
         self.st_o = Signal(reset_less=True)  # operation is a ST


@@ -130,11 +148,11 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
     Data (outputs)
     --------------
 
     Data (outputs)
     --------------

-    * :data_o:     Dest out (LD)          - managed by wr[0] go/req
-    * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
-    * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
+    * :o_data:  Dest out (LD)          - managed by wr[0] go/req
+    * :addr_o:  Address out (LD or ST) - managed by wr[1] go/req
+    * :exc_o:   Address/Data Exception occurred.  LD/ST must terminate

 
 

-    TODO: make addr_exc_o a data-type rather than a single-bit signal
+    TODO: make exc_o a data-type rather than a single-bit signal

           (see bug #302)
 
     Control Signals (In)
           (see bug #302)
 
     Control Signals (In)


@@ -177,7 +195,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         self.awid = awid
         self.pi = pi
         self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)
         self.awid = awid
         self.pi = pi
         self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)

-        self.debugtest = debugtest
+        self.debugtest = debugtest # enable debug output for unit testing

 
         # POWER-compliant LD/ST has index and update: *fixed* number of ports
         self.n_src = n_src = 3   # RA, RB, RT/RS
 
         # POWER-compliant LD/ST has index and update: *fixed* number of ports
         self.n_src = n_src = 3   # RA, RB, RT/RS


@@ -225,9 +243,9 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         self.oper_i = cu.oper_i
         self.src_i = cu._src_i
 
         self.oper_i = cu.oper_i
         self.src_i = cu._src_i
 

-        self.data_o = Data(self.data_wid, name="o")  # Dest1 out: RT
+        self.o_data = Data(self.data_wid, name="o")  # Dest1 out: RT

         self.addr_o = Data(self.data_wid, name="ea")  # Addr out: Update => RA
         self.addr_o = Data(self.data_wid, name="ea")  # Addr out: Update => RA

-        self.addr_exc_o = cu.addr_exc_o
+        self.exc_o = cu.exc_o

         self.done_o = cu.done_o
         self.busy_o = cu.busy_o
 
         self.done_o = cu.done_o
         self.busy_o = cu.busy_o
 


@@ -264,6 +282,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # opcode decode
         op_is_ld = Signal(reset_less=True)
         op_is_st = Signal(reset_less=True)
         # opcode decode
         op_is_ld = Signal(reset_less=True)
         op_is_st = Signal(reset_less=True)

+        op_is_dcbz = Signal(reset_less=True)
+        op_is_st_or_dcbz = Signal(reset_less=True)

 
         # ALU/LD data output control
         alu_valid = Signal(reset_less=True)  # ALU operands are valid
 
         # ALU/LD data output control
         alu_valid = Signal(reset_less=True)  # ALU operands are valid


@@ -274,6 +294,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         rda_any = Signal(reset_less=True)   # any read for address ops
         rd_done = Signal(reset_less=True)   # all *necessary* operands read
         wr_reset = Signal(reset_less=True)  # final reset condition
         rda_any = Signal(reset_less=True)   # any read for address ops
         rd_done = Signal(reset_less=True)   # all *necessary* operands read
         wr_reset = Signal(reset_less=True)  # final reset condition

+        canceln = Signal(reset_less=True)   # cancel (active low)

 
         # LD and ALU out
         alu_o = Signal(self.data_wid, reset_less=True)
 
         # LD and ALU out
         alu_o = Signal(self.data_wid, reset_less=True)


@@ -291,21 +312,33 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         reset_r = Signal(self.n_src, reset_less=True)  # reset src
         reset_s = Signal(reset_less=True)             # reset store
 
         reset_r = Signal(self.n_src, reset_less=True)  # reset src
         reset_s = Signal(reset_less=True)             # reset store
 

-        comb += reset_i.eq(issue_i | self.go_die_i)       # various
-        comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
-        comb += reset_w.eq(self.wr.go_i[0] | self.go_die_i)  # write reg 1
-        comb += reset_u.eq(self.wr.go_i[1] | self.go_die_i)  # update (reg 2)
-        comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
-        comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
-        comb += reset_a.eq(self.go_ad_i | self.go_die_i)
+        # end execution when a terminating condition is detected:
+        # - go_die_i: a speculative operation was cancelled
+        # - exc_o.happened: an exception has occurred
+        terminate = Signal()
+        comb += terminate.eq(self.go_die_i | self.exc_o.happened)
+
+        comb += reset_i.eq(issue_i | terminate)       # various
+        comb += reset_o.eq(self.done_o | terminate)      # opcode reset
+        comb += reset_w.eq(self.wr.go_i[0] | terminate)  # write reg 1
+        comb += reset_u.eq(self.wr.go_i[1] | terminate)  # update (reg 2)
+        comb += reset_s.eq(self.go_st_i | terminate)  # store reset
+        comb += reset_r.eq(self.rd.go_i | Repl(terminate, self.n_src))
+        comb += reset_a.eq(self.go_ad_i | terminate)

 
         p_st_go = Signal(reset_less=True)
         sync += p_st_go.eq(self.st.go_i)
 
         # decode bits of operand (latched)
         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 
         p_st_go = Signal(reset_less=True)
         sync += p_st_go.eq(self.st.go_i)
 
         # decode bits of operand (latched)
         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register

-        comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE)  # ST
-        comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD)  # LD
+        comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE)   # ST
+        comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD)    # LD
+        comb += op_is_dcbz.eq(oper_r.insn_type == MicrOp.OP_DCBZ)  # DCBZ
+        comb += op_is_st_or_dcbz.eq(op_is_st | op_is_dcbz)
+        # dcbz is special case of store
+        #uncomment if needed
+        #comb += Display("compldst_multi: op_is_dcbz = %i",
+        #                (oper_r.insn_type == MicrOp.OP_DCBZ))

         op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
         op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
         op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
         op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)


@@ -335,8 +368,9 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 
         # src operand latch
         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 
         # src operand latch

-        sync += src_l.s.eq(Repl(issue_i, self.n_src))
+        sync += src_l.s.eq(Repl(issue_i, self.n_src) & ~self.rdmaskn)

         sync += src_l.r.eq(reset_r)
         sync += src_l.r.eq(reset_r)

+        #### sync += Display("reset_r = %i",reset_r)

 
         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
         comb += alu_l.s.eq(reset_i)
 
         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
         comb += alu_l.s.eq(reset_i)


@@ -352,8 +386,10 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # dest operand latch
         comb += wri_l.s.eq(issue_i)
 
         # dest operand latch
         comb += wri_l.s.eq(issue_i)

-        sync += wri_l.r.eq(reset_w | Repl(self.done_o |
-                                          (self.pi.busy_o & op_is_update),
+        sync += wri_l.r.eq(reset_w | Repl(wr_reset |
+                                          (~self.pi.busy_o & op_is_update),
+                                          #(self.pi.busy_o & op_is_update),
+                            #self.done_o | (self.pi.busy_o & op_is_update),

                                           self.n_dst))
 
         # update-mode operand latch (EA written to reg 2)
                                           self.n_dst))
 
         # update-mode operand latch (EA written to reg 2)


@@ -361,7 +397,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         sync += upd_l.r.eq(reset_u)
 
         # store latch
         sync += upd_l.r.eq(reset_u)
 
         # store latch

-        comb += sto_l.s.eq(addr_ok & op_is_st)
+        comb += sto_l.s.eq(addr_ok & op_is_st_or_dcbz)

         sync += sto_l.r.eq(reset_s | p_st_go)
 
         # ld/st done.  needed to stop LD/ST from activating repeatedly
         sync += sto_l.r.eq(reset_s | p_st_go)
 
         # ld/st done.  needed to stop LD/ST from activating repeatedly


@@ -375,7 +411,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # create a latch/register for the operand
         with m.If(self.issue_i):
             sync += oper_r.eq(self.oper_i)
         # create a latch/register for the operand
         with m.If(self.issue_i):
             sync += oper_r.eq(self.oper_i)

-        with m.If(self.done_o):
+        with m.If(self.done_o | terminate):

             sync += oper_r.eq(0)
 
         # and for LD
             sync += oper_r.eq(0)
 
         # and for LD


@@ -403,13 +439,13 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 
         # select either immediate or src2 if opcode says so
         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 
         # select either immediate or src2 if opcode says so

-        op_is_imm = oper_r.imm_data.imm_ok
+        op_is_imm = oper_r.imm_data.ok

         src2_or_imm = Signal(self.data_wid, reset_less=True)
         src2_or_imm = Signal(self.data_wid, reset_less=True)

-        m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
+        m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.data, srl[1]))

 
         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
         comb += alu_o.eq(src1_or_z + src2_or_imm)  # actual EA
 
         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
         comb += alu_o.eq(src1_or_z + src2_or_imm)  # actual EA

-        m.d.sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
+        m.d.sync += alu_ok.eq(alu_valid & canceln) # keep ack in sync with EA

 
         ############################
         # Control Signal calculation
 
         ############################
         # Control Signal calculation


@@ -420,15 +456,16 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # 1st operand read-request only when zero not active
         # 2nd operand only needed when immediate is not active
 
         # 1st operand read-request only when zero not active
         # 2nd operand only needed when immediate is not active

-        slg = Cat(op_is_z, op_is_imm)
+        slg = Cat(op_is_z, op_is_imm) #is this correct ?

         bro = Repl(self.busy_o, self.n_src)
         bro = Repl(self.busy_o, self.n_src)

-        comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
+        comb += self.rd.rel_o.eq(src_l.q & bro & ~slg)

 
         # note when the address-related read "go" signals are active
         comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
 
         # alu input valid when 1st and 2nd ops done (or imm not active)
 
         # note when the address-related read "go" signals are active
         comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
 
         # alu input valid when 1st and 2nd ops done (or imm not active)

-        comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]))
+        comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]) &
+                             canceln)

 
         # 3rd operand only needed when operation is a store
         comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
 
         # 3rd operand only needed when operation is a store
         comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)


@@ -439,33 +476,39 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # address release only if addr ready, but Port must be idle
         comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
 
         # address release only if addr ready, but Port must be idle
         comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
 

+        # the write/store (etc) all must be cancelled if an exception occurs
+        # note: cancel is active low, like shadown_i,
+        #       while exc_o.happpened is active high
+        comb += canceln.eq(~self.exc_o.happened & self.shadown_i)
+

         # store release when st ready *and* all operands read (and no shadow)
         # store release when st ready *and* all operands read (and no shadow)

-        comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st &
-                               self.shadown_i)
+        # dcbz is special case of store -- TODO verify shadows
+        comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st_or_dcbz &
+                               canceln)

 
         # request write of LD result.  waits until shadow is dropped.
         comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
 
         # request write of LD result.  waits until shadow is dropped.
         comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &

-                                  op_is_ld & self.shadown_i)
+                                  op_is_ld & canceln)

 
         # request write of EA result only in update mode
         comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
 
         # request write of EA result only in update mode
         comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &

-                                  alu_valid & self.shadown_i)
+                                  alu_valid & canceln)

 
         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
         comb += wr_any.eq(self.st.go_i | p_st_go |
                           self.wr.go_i[0] | self.wr.go_i[1])
 
         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
         comb += wr_any.eq(self.st.go_i | p_st_go |
                           self.wr.go_i[0] | self.wr.go_i[1])

-        comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
+        comb += wr_reset.eq(rst_l.q & busy_o & canceln &

                             ~(self.st.rel_o | self.wr.rel_o[0] |
                               self.wr.rel_o[1]) &
                             ~(self.st.rel_o | self.wr.rel_o[0] |
                               self.wr.rel_o[1]) &

-                            (lod_l.qn | op_is_st) &
-                            (~self.pi.busy_o | op_is_ld))
-        comb += self.done_o.eq(wr_reset)
+                            (lod_l.qn | op_is_st_or_dcbz)
+                            )
+        comb += self.done_o.eq(wr_reset & (~self.pi.busy_o | op_is_ld))

 
         ######################
         # Data/Address outputs
 
         # put the LD-output register directly onto the output bus on a go_write
 
         ######################
         # Data/Address outputs
 
         # put the LD-output register directly onto the output bus on a go_write

-        comb += self.data_o.data.eq(self.dest[0])
+        comb += self.o_data.data.eq(self.dest[0])

         with m.If(self.wr.go_i[0]):
             comb += self.dest[0].eq(ldd_r)
 
         with m.If(self.wr.go_i[0]):
             comb += self.dest[0].eq(ldd_r)
 


@@ -484,13 +527,26 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # connect to LD/ST PortInterface.
         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 
         # connect to LD/ST PortInterface.
         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD

-        comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
+        comb += pi.is_st_i.eq(op_is_st_or_dcbz & busy_o)  # decoded-ST
+        comb += pi.is_dcbz_i.eq(op_is_dcbz & busy_o)  # decoded-DCBZ

         comb += pi.data_len.eq(oper_r.data_len)  # data_len
         # address: use sync to avoid long latency
         sync += pi.addr.data.eq(addr_r)           # EA from adder
         comb += pi.data_len.eq(oper_r.data_len)  # data_len
         # address: use sync to avoid long latency
         sync += pi.addr.data.eq(addr_r)           # EA from adder

+        with m.If(op_is_dcbz):
+            sync += Display("LDSTCompUnit.DCBZ: EA from adder %x", addr_r)
+

         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)

-        comb += self.addr_exc_o.eq(pi.addr_exc_o)  # exception occurred
+        comb += self.exc_o.eq(pi.exc_o)  # exception occurred

         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine

+        # connect MSR.PR etc. for priv/virt operation
+        comb += pi.priv_mode.eq(~oper_r.msr[MSR.PR])
+        comb += pi.virt_mode.eq(oper_r.msr[MSR.DR])
+        comb += pi.mode_32bit.eq(~oper_r.msr[MSR.SF])
+        sync += Display("LDSTCompUnit: oper_r.msr %x pr=%x dr=%x sf=%x",
+                                      oper_r.msr,
+                                      oper_r.msr[MSR.PR],
+                                      oper_r.msr[MSR.DR],
+                                      oper_r.msr[MSR.SF])

 
         # byte-reverse on LD
         revnorev = Signal(64, reset_less=True)
 
         # byte-reverse on LD
         revnorev = Signal(64, reset_less=True)


@@ -504,7 +560,11 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # then check sign-extend
         with m.If(oper_r.sign_extend):
 
         # then check sign-extend
         with m.If(oper_r.sign_extend):

-            comb += ldd_o.eq(exts(revnorev, 32, 64))  # sign-extend
+            # okok really should "if data_len == 4" and so on here
+            with m.If(oper_r.data_len == 2):
+                comb += ldd_o.eq(exts(revnorev, 16, 64))  # sign-extend hword
+            with m.Else():
+                comb += ldd_o.eq(exts(revnorev, 32, 64))  # sign-extend dword

         with m.Else():
             comb += ldd_o.eq(revnorev)
 
         with m.Else():
             comb += ldd_o.eq(revnorev)
 


@@ -526,11 +586,13 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         return m
 
     def get_out(self, i):
         return m
 
     def get_out(self, i):

-        """make LDSTCompUnit look like RegSpecALUAPI"""
+        """make LDSTCompUnit look like RegSpecALUAPI.  these correspond
+        to LDSTOutputData o and o1 respectively.
+        """

         if i == 0:
         if i == 0:

-            return self.data_o
+            return self.o_data # LDSTOutputData.regspec o

         if i == 1:
         if i == 1:

-            return self.addr_o
+            return self.addr_o # LDSTOutputData.regspec o1

         # return self.dest[i]
 
     def get_fu_out(self, i):
         # return self.dest[i]
 
     def get_fu_out(self, i):


@@ -551,7 +613,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         yield self.adr_rel_o
         yield self.sto_rel_o
         yield self.wr.rel_o
         yield self.adr_rel_o
         yield self.sto_rel_o
         yield self.wr.rel_o

-        yield from self.data_o.ports()
+        yield from self.o_data.ports()

         yield from self.addr_o.ports()
         yield self.load_mem_o
         yield self.stwd_mem_o
         yield from self.addr_o.ports()
         yield self.load_mem_o
         yield self.stwd_mem_o


@@ -582,9 +644,9 @@ def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
     yield dut.src1_i.eq(src1)
     yield dut.src2_i.eq(src2)
     yield dut.src3_i.eq(src3)
     yield dut.src1_i.eq(src1)
     yield dut.src2_i.eq(src2)
     yield dut.src3_i.eq(src3)

-    yield dut.oper_i.imm_data.imm.eq(imm)
-    yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
-    yield dut.oper_i.update.eq(update)
+    yield dut.oper_i.imm_data.data.eq(imm)
+    yield dut.oper_i.imm_data.ok.eq(imm_ok)
+    #guess: this one was removed -- yield dut.oper_i.update.eq(update)

     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)


@@ -599,9 +661,9 @@ def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
         if rel == active_rel:
             break
         yield
         if rel == active_rel:
             break
         yield

-    yield dut.rd.go.eq(active_rel)
+    yield dut.rd.go_i.eq(active_rel)

     yield
     yield

-    yield dut.rd.go.eq(0)
+    yield dut.rd.go_i.eq(0)

 
     yield from wait_for(dut.adr_rel_o, False, test1st=True)
     # yield from wait_for(dut.adr_rel_o)
 
     yield from wait_for(dut.adr_rel_o, False, test1st=True)
     # yield from wait_for(dut.adr_rel_o)


@@ -638,8 +700,8 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
     yield dut.src1_i.eq(src1)
     yield dut.src2_i.eq(src2)
     yield dut.oper_i.zero_a.eq(zero_a)
     yield dut.src1_i.eq(src1)
     yield dut.src2_i.eq(src2)
     yield dut.oper_i.zero_a.eq(zero_a)

-    yield dut.oper_i.imm_data.imm.eq(imm)
-    yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
+    yield dut.oper_i.imm_data.data.eq(imm)
+    yield dut.oper_i.imm_data.ok.eq(imm_ok)

     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)


@@ -654,9 +716,9 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
 
     # wait for the operands (RA, RB, or both)
     if rd:
 
     # wait for the operands (RA, RB, or both)
     if rd:

-        yield dut.rd.go.eq(rd)
+        yield dut.rd.go_i.eq(rd)

         yield from wait_for(dut.rd.rel_o)
         yield from wait_for(dut.rd.rel_o)

-        yield dut.rd.go.eq(0)
+        yield dut.rd.go_i.eq(0)

 
     yield from wait_for(dut.adr_rel_o, False, test1st=True)
     # yield dut.ad.go.eq(1)
 
     yield from wait_for(dut.adr_rel_o, False, test1st=True)
     # yield dut.ad.go.eq(1)


@@ -665,24 +727,24 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
 
     if update:
         yield from wait_for(dut.wr.rel_o[1])
 
     if update:
         yield from wait_for(dut.wr.rel_o[1])

-        yield dut.wr.go.eq(0b10)
+        yield dut.wr.go_i.eq(0b10)

         yield
         addr = yield dut.addr_o
         print("addr", addr)
         yield
         addr = yield dut.addr_o
         print("addr", addr)

-        yield dut.wr.go.eq(0)
+        yield dut.wr.go_i.eq(0)

     else:
         addr = None
 
     yield from wait_for(dut.wr.rel_o[0], test1st=True)
     else:
         addr = None
 
     yield from wait_for(dut.wr.rel_o[0], test1st=True)

-    yield dut.wr.go.eq(1)
+    yield dut.wr.go_i.eq(1)

     yield
     yield

-    data = yield dut.data_o
-    print(data)
-    yield dut.wr.go.eq(0)
+    data = yield dut.o_data.o
+    data_ok = yield dut.o_data.o_ok
+    yield dut.wr.go_i.eq(0)

     yield from wait_for(dut.busy_o)
     yield
     # wait_for(dut.stwd_mem_o)
     yield from wait_for(dut.busy_o)
     yield
     # wait_for(dut.stwd_mem_o)

-    return data, addr
+    return data, data_ok, addr

 
 
 def ldst_sim(dut):
 
 
 def ldst_sim(dut):


@@ -722,22 +784,31 @@ def ldst_sim(dut):
 
 class TestLDSTCompUnit(LDSTCompUnit):
 
 
 class TestLDSTCompUnit(LDSTCompUnit):
 

-    def __init__(self, rwid):
+    def __init__(self, rwid, pspec):

         from soc.experiment.l0_cache import TstL0CacheBuffer
         from soc.experiment.l0_cache import TstL0CacheBuffer

-        self.l0 = l0 = TstL0CacheBuffer()
-        pi = l0.l0.dports[0].pi
+        self.l0 = l0 = TstL0CacheBuffer(pspec)
+        pi = l0.l0.dports[0]

         LDSTCompUnit.__init__(self, pi, rwid, 4)
 
     def elaborate(self, platform):
         m = LDSTCompUnit.elaborate(self, platform)
         m.submodules.l0 = self.l0
         LDSTCompUnit.__init__(self, pi, rwid, 4)
 
     def elaborate(self, platform):
         m = LDSTCompUnit.elaborate(self, platform)
         m.submodules.l0 = self.l0

-        m.d.comb += self.ad.go.eq(self.ad.rel)  # link addr-go direct to rel
+        # link addr-go direct to rel
+        m.d.comb += self.ad.go_i.eq(self.ad.rel_o)

         return m
 
 
 def test_scoreboard():
 
         return m
 
 
 def test_scoreboard():
 

-    dut = TestLDSTCompUnit(16)
+    units = {}
+    pspec = TestMemPspec(ldst_ifacetype='bare_wb',
+                         imem_ifacetype='bare_wb',
+                         addr_wid=48,
+                         mask_wid=8,
+                         reg_wid=64,
+                         units=units)
+
+    dut = TestLDSTCompUnit(16,pspec)

     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_ldst_comp.il", "w") as f:
         f.write(vl)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_ldst_comp.il", "w") as f:
         f.write(vl)


@@ -747,24 +818,33 @@ def test_scoreboard():
 
 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 
 
 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 

-    def __init__(self):
+    def __init__(self, pspec):

         from soc.experiment.l0_cache import TstL0CacheBuffer
         from soc.fu.ldst.pipe_data import LDSTPipeSpec
         regspec = LDSTPipeSpec.regspec
         from soc.experiment.l0_cache import TstL0CacheBuffer
         from soc.fu.ldst.pipe_data import LDSTPipeSpec
         regspec = LDSTPipeSpec.regspec

-        self.l0 = l0 = TstL0CacheBuffer()
-        pi = l0.l0.dports[0].pi
+        self.l0 = l0 = TstL0CacheBuffer(pspec)
+        pi = l0.l0.dports[0]

         LDSTCompUnit.__init__(self, pi, regspec, 4)
 
     def elaborate(self, platform):
         m = LDSTCompUnit.elaborate(self, platform)
         m.submodules.l0 = self.l0
         LDSTCompUnit.__init__(self, pi, regspec, 4)
 
     def elaborate(self, platform):
         m = LDSTCompUnit.elaborate(self, platform)
         m.submodules.l0 = self.l0

-        m.d.comb += self.ad.go.eq(self.ad.rel)  # link addr-go direct to rel
+        # link addr-go direct to rel
+        m.d.comb += self.ad.go_i.eq(self.ad.rel_o)

         return m
 
 
 def test_scoreboard_regspec():
 
         return m
 
 
 def test_scoreboard_regspec():
 

-    dut = TestLDSTCompUnitRegSpec()
+    units = {}
+    pspec = TestMemPspec(ldst_ifacetype='bare_wb',
+                         imem_ifacetype='bare_wb',
+                         addr_wid=48,
+                         mask_wid=8,
+                         reg_wid=64,
+                         units=units)
+
+    dut = TestLDSTCompUnitRegSpec(pspec)

     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_ldst_comp.il", "w") as f:
         f.write(vl)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_ldst_comp.il", "w") as f:
         f.write(vl)