- comb += reset_i.eq(issue_i | self.go_die_i) # various
- comb += reset_o.eq(wr_reset | self.go_die_i) # opcode reset
- comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
- comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
- comb += reset_s.eq(self.go_st_i | self.go_die_i) # store reset
- comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
- comb += reset_a.eq(self.go_ad_i | self.go_die_i)
+ # end execution when a terminating condition is detected:
+ # - go_die_i: a speculative operation was cancelled
+ # - exc_o.happened: an exception has occurred
+ terminate = Signal()
+ comb += terminate.eq(self.go_die_i | self.exc_o.happened)
+
+ comb += reset_i.eq(issue_i | terminate) # various
+ comb += reset_o.eq(self.done_o | terminate) # opcode reset
+ comb += reset_w.eq(self.wr.go_i[0] | terminate) # write reg 1
+ comb += reset_u.eq(self.wr.go_i[1] | terminate) # update (reg 2)
+ comb += reset_s.eq(self.go_st_i | terminate) # store reset
+ comb += reset_r.eq(self.rd.go_i | Repl(terminate, self.n_src))
+ comb += reset_a.eq(self.go_ad_i | terminate)
+
+ p_st_go = Signal(reset_less=True)
+ sync += p_st_go.eq(self.st.go_i)
+
+ # decode bits of operand (latched)
+ oper_r = CompLDSTOpSubset(name="oper_r") # Dest register
+ comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
+ comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD
+ comb += op_is_dcbz.eq(oper_r.insn_type == MicrOp.OP_DCBZ) # DCBZ
+ comb += op_is_st_or_dcbz.eq(op_is_st | op_is_dcbz)
+ # dcbz is special case of store
+ #uncomment if needed
+ #comb += Display("compldst_multi: op_is_dcbz = %i",
+ # (oper_r.insn_type == MicrOp.OP_DCBZ))
+ op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE
+ op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit
+ comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
+ comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
+ comb += self.ld_o.eq(op_is_ld)
+ comb += self.st_o.eq(op_is_st)