+class DTLBUpdate(Elaboratable):
+ def __init__(self):
+ self.tlbie = Signal()
+ self.tlbwe = Signal()
+ self.doall = Signal()
+ self.updated = Signal()
+ self.v_updated = Signal()
+ self.tlb_hit = Signal()
+ self.tlb_req_index = Signal(TLB_SET_BITS)
+
+ self.tlb_hit_way = Signal(TLB_WAY_BITS)
+ self.tlb_tag_way = Signal(TLB_TAG_WAY_BITS)
+ self.tlb_pte_way = Signal(TLB_PTE_WAY_BITS)
+ self.repl_way = Signal(TLB_WAY_BITS)
+ self.eatag = Signal(TLB_EA_TAG_BITS)
+ self.pte_data = Signal(TLB_PTE_BITS)
+
+ self.dv = Signal(TLB_NUM_WAYS) # tlb_way_valids_t
+
+ self.tb_out = Signal(TLB_TAG_WAY_BITS) # tlb_way_tags_t
+ self.db_out = Signal(TLB_NUM_WAYS) # tlb_way_valids_t
+ self.pb_out = Signal(TLB_PTE_WAY_BITS) # tlb_way_ptes_t
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+ sync = m.d.sync
+
+ tagset = Signal(TLB_TAG_WAY_BITS)
+ pteset = Signal(TLB_PTE_WAY_BITS)
+
+ tb_out, pb_out, db_out = self.tb_out, self.pb_out, self.db_out
+ comb += db_out.eq(self.dv)
+
+ with m.If(self.tlbie & self.doall):
+ pass # clear all back in parent
+ with m.Elif(self.tlbie):
+ with m.If(self.tlb_hit):
+ comb += db_out.bit_select(self.tlb_hit_way, 1).eq(0)
+ comb += self.v_updated.eq(1)
+
+ with m.Elif(self.tlbwe):
+
+ comb += tagset.eq(self.tlb_tag_way)
+ comb += write_tlb_tag(self.repl_way, tagset, self.eatag)
+ comb += tb_out.eq(tagset)
+
+ comb += pteset.eq(self.tlb_pte_way)
+ comb += write_tlb_pte(self.repl_way, pteset, self.pte_data)
+ comb += pb_out.eq(pteset)
+
+ comb += db_out.bit_select(self.repl_way, 1).eq(1)
+
+ comb += self.updated.eq(1)
+ comb += self.v_updated.eq(1)
+
+ return m
+
+
+class DCachePendingHit(Elaboratable):
+
+ def __init__(self, tlb_pte_way, tlb_valid_way, tlb_hit_way,
+ cache_i_validdx, cache_tag_set,
+ req_addr,
+ hit_set):
+
+ self.go = Signal()
+ self.virt_mode = Signal()
+ self.is_hit = Signal()
+ self.tlb_hit = Signal()
+ self.hit_way = Signal(WAY_BITS)
+ self.rel_match = Signal()
+ self.req_index = Signal(INDEX_BITS)
+ self.reload_tag = Signal(TAG_BITS)
+
+ self.tlb_hit_way = tlb_hit_way
+ self.tlb_pte_way = tlb_pte_way
+ self.tlb_valid_way = tlb_valid_way
+ self.cache_i_validdx = cache_i_validdx
+ self.cache_tag_set = cache_tag_set
+ self.req_addr = req_addr
+ self.hit_set = hit_set
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+ sync = m.d.sync
+
+ go = self.go
+ virt_mode = self.virt_mode
+ is_hit = self.is_hit
+ tlb_pte_way = self.tlb_pte_way
+ tlb_valid_way = self.tlb_valid_way
+ cache_i_validdx = self.cache_i_validdx
+ cache_tag_set = self.cache_tag_set
+ req_addr = self.req_addr
+ tlb_hit_way = self.tlb_hit_way
+ tlb_hit = self.tlb_hit
+ hit_set = self.hit_set
+ hit_way = self.hit_way
+ rel_match = self.rel_match
+ req_index = self.req_index
+ reload_tag = self.reload_tag
+
+ rel_matches = Array(Signal(name="rel_matches_%d" % i) \
+ for i in range(TLB_NUM_WAYS))
+ hit_way_set = HitWaySet()
+
+ # Test if pending request is a hit on any way
+ # In order to make timing in virtual mode,
+ # when we are using the TLB, we compare each
+ # way with each of the real addresses from each way of
+ # the TLB, and then decide later which match to use.
+
+ with m.If(virt_mode):
+ for j in range(TLB_NUM_WAYS): # tlb_num_way_t
+ s_tag = Signal(TAG_BITS, name="s_tag%d" % j)
+ s_hit = Signal()
+ s_pte = Signal(TLB_PTE_BITS)
+ s_ra = Signal(REAL_ADDR_BITS)
+ comb += s_pte.eq(read_tlb_pte(j, tlb_pte_way))
+ comb += s_ra.eq(Cat(req_addr[0:TLB_LG_PGSZ],
+ s_pte[TLB_LG_PGSZ:REAL_ADDR_BITS]))
+ comb += s_tag.eq(get_tag(s_ra))
+
+ for i in range(NUM_WAYS): # way_t
+ is_tag_hit = Signal(name="is_tag_hit_%d_%d" % (j, i))
+ comb += is_tag_hit.eq(go & cache_i_validdx[i] &
+ (read_tag(i, cache_tag_set) == s_tag)
+ & tlb_valid_way[j])
+ with m.If(is_tag_hit):
+ comb += hit_way_set[j].eq(i)
+ comb += s_hit.eq(1)
+ comb += hit_set[j].eq(s_hit)
+ with m.If(s_tag == reload_tag):
+ comb += rel_matches[j].eq(1)
+ with m.If(tlb_hit):
+ comb += is_hit.eq(hit_set[tlb_hit_way])
+ comb += hit_way.eq(hit_way_set[tlb_hit_way])
+ comb += rel_match.eq(rel_matches[tlb_hit_way])
+ with m.Else():
+ s_tag = Signal(TAG_BITS)
+ comb += s_tag.eq(get_tag(req_addr))
+ for i in range(NUM_WAYS): # way_t
+ is_tag_hit = Signal(name="is_tag_hit_%d" % i)
+ comb += is_tag_hit.eq(go & cache_i_validdx[i] &
+ (read_tag(i, cache_tag_set) == s_tag))
+ with m.If(is_tag_hit):
+ comb += hit_way.eq(i)
+ comb += is_hit.eq(1)
+ with m.If(s_tag == reload_tag):
+ comb += rel_match.eq(1)
+
+ return m
+
+