LDSTCompUnit test data structures linked up, starting debugging

[soc.git] / src / soc / experiment / l0_cache.py

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 3e2c453c5a936a1e8b51ae914e14d1d3559f1da7..09d0e5f18343f1186040da259cde94e5f03fa558 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -15,7 +15,7 @@ Links:
 
 """
 
 
 """
 

-from nmigen.compat.sim import run_simulation
+from nmigen.compat.sim import run_simulation, Settle

 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
 from nmutil.iocontrol import RecordObject
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
 from nmutil.iocontrol import RecordObject


@@ -113,7 +113,7 @@ class PortInterface(RecordObject):
         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 
         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 

-# TODO:
+# TODO: elaborate function

 
 
 class DualPortSplitter(Elaboratable):
 
 
 class DualPortSplitter(Elaboratable):


@@ -128,8 +128,23 @@ class DualPortSplitter(Elaboratable):
 
     once that is done each pair of ports may be wired directly
     to the dual ports of L0CacheBuffer
 
     once that is done each pair of ports may be wired directly
     to the dual ports of L0CacheBuffer

+
+    The split is carried out so that, regardless of alignment or
+    mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
+    of the address, whilst outgoing PortInterface[1] takes
+    bit 4 == 1.
+
+    PortInterface *may* need to be changed so that the length is
+    a binary number (accepting values 1-16).

     """
     """

-    pass
+    def __init__(self):
+        self.outp = []
+        self.outp[0] = PortInterface(name="outp_0")
+        self.outp[1] = PortInterface(name="outp_1")
+        self.inp     = PortInterface(name="inp")
+
+    def elaborate(self, platform):
+        splitter = LDSTSplitter(64, 48, 4)

 
 
 class DataMergerRecord(Record):
 
 
 class DataMergerRecord(Record):


@@ -532,16 +547,19 @@ def l0_cache_ldst(dut):
 def data_merger_merge(dut):
     print("data_merger")
     #starting with all inputs zero
 def data_merger_merge(dut):
     print("data_merger")
     #starting with all inputs zero

+    yield Settle()

     en = yield dut.data_o.en
     data = yield dut.data_o.data
     assert en == 0, "en must be zero"
     assert data == 0, "data must be zero"
     yield
     en = yield dut.data_o.en
     data = yield dut.data_o.data
     assert en == 0, "en must be zero"
     assert data == 0, "data must be zero"
     yield

+

     yield dut.addr_array_i[0].eq(0xFF)
     for j in range(dut.array_size):
         yield dut.data_i[j].en.eq(1 << j)
         yield dut.data_i[j].data.eq(0xFF << (16*j))
     yield dut.addr_array_i[0].eq(0xFF)
     for j in range(dut.array_size):
         yield dut.data_i[j].en.eq(1 << j)
         yield dut.data_i[j].data.eq(0xFF << (16*j))

-    yield
+    yield Settle()
+

     en = yield dut.data_o.en
     data = yield dut.data_o.data
     assert data == 0xff00ff00ff00ff00ff00ff00ff00ff
     en = yield dut.data_o.en
     data = yield dut.data_o.data
     assert data == 0xff00ff00ff00ff00ff00ff00ff00ff


@@ -551,9 +569,9 @@ def data_merger_merge(dut):
 def test_l0_cache():
 
     dut = TstL0CacheBuffer()
 def test_l0_cache():
 
     dut = TstL0CacheBuffer()

-    vl = rtlil.convert(dut, ports=dut.ports())
-    with open("test_basic_l0_cache.il", "w") as f:
-        f.write(vl)
+    #vl = rtlil.convert(dut, ports=dut.ports())
+    #with open("test_basic_l0_cache.il", "w") as f:
+    #    f.write(vl)

 
     run_simulation(dut, l0_cache_ldst(dut),
                    vcd_name='test_l0_cache_basic.vcd')
 
     run_simulation(dut, l0_cache_ldst(dut),
                    vcd_name='test_l0_cache_basic.vcd')