-# if l_in.addr(63) = '0' then
-# pgtbl := r.pgtbl0;
-# pt_valid := r.pt0_valid;
- with m.If(~l_in.addr[63]):
- comb += pgtbl.eq(r.pgtbl0)
- comb += pt_valid.eq(r.pt0_valid)
-# else
-# pgtbl := r.pgtbl3;
-# pt_valid := r.pt3_valid;
- with m.Else():
- comb += pgtbl.eq(r.pt3_valid)
- comb += pt_valid.eq(r.pt3_valid)
-# end if;
-
-# -- rts == radix tree size, # address bits being
-# -- translated
-# rts := unsigned('0' & pgtbl(62 downto 61) &
-# pgtbl(7 downto 5));
- # rts == radix tree size, number of address bits
- # being translated
- comb += rts.eq((Cat(
- Cat(
- pgtbl[5:8],
- pgtbl[61:63]
- ),
- Const(0b0,1)
- )).as_unsigned())
-
-# -- mbits == # address bits to index top level
-# -- of tree
-# mbits := unsigned('0' & pgtbl(4 downto 0));
- # mbits == number of address bits to index top
- # level of tree
- comb += mbits.eq((
- Cat(pgtbl[0:5], Const(0b0, 1))
- ).as_unsigned())
-# -- set v.shift to rts so that we can use finalmask
-# -- for the segment check
-# v.shift := rts;
-# v.mask_size := mbits(4 downto 0);
-# v.pgbase := pgtbl(55 downto 8) & x"00";
- # set v.shift to rts so that we can use finalmask
- # for the segment check
- comb += v.shift.eq(rts)
- comb += v.mask_size.eq(mbits[0:5])
- comb += v.pgbase.eq(Cat(
- Cont(0x00, 2),
- pgtbl[8:56]
- ))
-
-# if l_in.valid = '1' then
- with m.If(l_in.valid):
-# v.addr := l_in.addr;
-# v.iside := l_in.iside;
-# v.store := not (l_in.load or l_in.iside);
-# v.priv := l_in.priv;
- comb += v.addr.eq(l_in.addr
- comb += v.iside.eq(l_in.iside)
- comb += v.store.eq(~(l_in.load | l_in.siside))
-# if l_in.tlbie = '1' then
- with m.If(l_in.tlbie):
-# -- Invalidate all iTLB/dTLB entries for
-# -- tlbie with RB[IS] != 0 or RB[AP] != 0,
-# -- or for slbia
-# v.inval_all := l_in.slbia or l_in.addr(11)
-# or l_in.addr(10) or
-# l_in.addr(7) or l_in.addr(6)
-# or l_in.addr(5);
- # Invalidate all iTLB/dTLB entries for
- # tlbie with RB[IS] != 0 or RB[AP] != 0,
- # or for slbia
- comb += v.inval_all.eq(l_in.slbia
- | l_in.addr[11]
- | l_in.addr[10]
- | l_in.addr[7]
- | l_in.addr[6]
- | l_in.addr[5]
- )
-# -- The RIC field of the tlbie instruction
-# -- comes across on the sprn bus as bits 2--3.
-# -- RIC=2 flushes process table caches.
-# if l_in.sprn(3) = '1' then
- # The RIC field of the tlbie instruction
- # comes across on the sprn bus as bits 2--3.
- # RIC=2 flushes process table caches.
- with m.If(l_in.sprn[3]):
-# v.pt0_valid := '0';
-# v.pt3_valid := '0';
- comb += v.pt0_valid.eq(0)
- comb += v.pt3_valid.eq(0)
-# end if;
-# v.state := DO_TLBIE;
- comb += v.state.eq(State.DO_TLBIE)
-# else
- with m.Else():
-# v.valid := '1';
- comb += v.valid.eq(1)
-# if pt_valid = '0' then
- with m.If(~pt_valid):
-# -- need to fetch process table entry
-# -- set v.shift so we can use finalmask
-# -- for generating the process table
-# -- entry address
-# v.shift := unsigned('0' & r.prtbl(
-# 4 downto 0));
-# v.state := PROC_TBL_READ;
- # need to fetch process table entry
- # set v.shift so we can use finalmask
- # for generating the process table
- # entry address
- comb += v.shift.eq((Cat(
- r.prtble[0:5],
- Const(0b0, 1)
- )).as_unsigned())
- comb += v.state.eq(State.PROC_TBL_READ)
-
-# elsif mbits = 0 then
- with m.If(~mbits):
-# -- Use RPDS = 0 to disable radix
-# -- tree walks
-# v.state := RADIX_FINISH;
-# v.invalid := '1';
- # Use RPDS = 0 to disable radix
- # tree walks
- comb += v.state.eq(State.RADIX_FINISH)
- comb += v.invalid.eq(1)
-# else
- with m.Else():
-# v.state := SEGMENT_CHECK;
- comb += v.state.eq(State.SEGMENT_CHECK)
-# end if;
-# end if;
-# end if;
-
-# if l_in.mtspr = '1' then
- with m.If(l_in.mtspr):
-# -- Move to PID needs to invalidate L1 TLBs
-# -- and cached pgtbl0 value. Move to PRTBL
-# -- does that plus invalidating the cached
-# -- pgtbl3 value as well.
-# if l_in.sprn(9) = '0' then
- # Move to PID needs to invalidate L1 TLBs
- # and cached pgtbl0 value. Move to PRTBL
- # does that plus invalidating the cached
- # pgtbl3 value as well.
- with m.If(~l_in.sprn[9]):
-# v.pid := l_in.rs(31 downto 0);
- comb += v.pid.eq(l_in.rs[0:32])
-# else
- with m.Else():
-# v.prtbl := l_in.rs;
-# v.pt3_valid := '0';
- comb += v.prtbl.eq(l_in.rs)
- comb += v.pt3_valid.eq(0)
-# end if;
-
-# v.pt0_valid := '0';
-# v.inval_all := '1';
-# v.state := DO_TLBIE;
- comb += v.pt0_valid.eq(0)
- comb += v.inval_all.eq(0)
- comb += v.state.eq(State.DO_TLBIE)
-# end if;