- return m
-
- def ports(self):
- for p in self.dports:
- yield from p.ports()
-
-
-def wait_busy(port, no=False):
- while True:
- busy = yield port.pi.busy_o
- print("busy", no, busy)
- if bool(busy) == no:
- break
- yield
-
-
-def wait_addr(port):
- while True:
- addr_ok = yield port.pi.addr_ok_o
- print("addrok", addr_ok)
- if not addr_ok:
- break
- yield
-
-
-def wait_ldok(port):
- while True:
- ldok = yield port.pi.ld.ok
- print("ldok", ldok)
- if ldok:
- break
- yield
-
-
-def l0_cache_st(dut, addr, data, datalen):
- mem = dut.mem
- port1 = dut.pi
-
- # have to wait until not busy
- yield from wait_busy(port1, no=False) # wait until not busy
-
- # set up a ST on the port. address first:
- yield port1.pi.is_st_i.eq(1) # indicate ST
- yield port1.pi.data_len.eq(datalen) # ST length (1/2/4/8)
-
- yield port1.pi.addr.data.eq(addr) # set address
- yield port1.pi.addr.ok.eq(1) # set ok
- yield from wait_addr(port1) # wait until addr ok
- # yield # not needed, just for checking
- # yield # not needed, just for checking
- # assert "ST" for one cycle (required by the API)
- yield port1.pi.st.data.eq(data)
- yield port1.pi.st.ok.eq(1)
- yield
- yield port1.pi.st.ok.eq(0)
-
- # can go straight to reset.
- yield port1.pi.is_st_i.eq(0) # end
- yield port1.pi.addr.ok.eq(0) # set !ok
- # yield from wait_busy(port1, False) # wait until not busy
-
-
-def l0_cache_ld(dut, addr, datalen, expected):