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add build commands to Makefile for versa ecp5
[soc.git]
/
src
/
soc
/
experiment
/
sim.py
diff --git
a/src/soc/experiment/sim.py
b/src/soc/experiment/sim.py
index 66b37ee878b424ebccb23029ca0afed1fe788a8a..aebb51de404f11d51aa2006f5ee0109f773e972f 100644
(file)
--- a/
src/soc/experiment/sim.py
+++ b/
src/soc/experiment/sim.py
@@
-1,4
+1,4
@@
-from soc.decoder.power_enums import
Internal
Op
+from soc.decoder.power_enums import
Micr
Op
from random import randint, seed
from copy import deepcopy
from random import randint, seed
from copy import deepcopy
@@
-8,16
+8,15
@@
from math import log
class MemSim:
def __init__(self, regwid, addrw):
self.regwid = regwid
class MemSim:
def __init__(self, regwid, addrw):
self.regwid = regwid
- self.ddepth = 1 # regwid//8
- depth = (1
<<
addrw) // self.ddepth
+ self.ddepth = 1
# regwid//8
+ depth = (1
<<
addrw) // self.ddepth
self.mem = list(range(0, depth))
def ld(self, addr):
self.mem = list(range(0, depth))
def ld(self, addr):
- return self.mem[addr
>>
self.ddepth]
+ return self.mem[addr
>>
self.ddepth]
def st(self, addr, data):
def st(self, addr, data):
- self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
-
+ self.mem[addr >> self.ddepth] = data & ((1 << self.regwid)-1)
IADD = 0
IADD = 0
@@
-36,16
+35,18
@@
class RegSim:
self.regs = [0] * nregs
def op(self, op, op_imm, imm, src1, src2, dest):
self.regs = [0] * nregs
def op(self, op, op_imm, imm, src1, src2, dest):
+ print("regsim op src1, src2", op, op_imm, imm, src1, src2, dest)
maxbits = (1 << self.rwidth) - 1
src1 = self.regs[src1] & maxbits
if op_imm:
src2 = imm
else:
src2 = self.regs[src2] & maxbits
maxbits = (1 << self.rwidth) - 1
src1 = self.regs[src1] & maxbits
if op_imm:
src2 = imm
else:
src2 = self.regs[src2] & maxbits
- if op ==
Internal
Op.OP_ADD:
+ if op ==
Micr
Op.OP_ADD:
val = src1 + src2
val = src1 + src2
- elif op ==
Internal
Op.OP_MUL_L64:
+ elif op ==
Micr
Op.OP_MUL_L64:
val = src1 * src2
val = src1 * src2
+ print("mul src1, src2", src1, src2, val)
elif op == ISUB:
val = src1 - src2
elif op == ISHF:
elif op == ISUB:
val = src1 - src2
elif op == ISHF:
@@
-59,13
+60,13
@@
class RegSim:
elif op == IBNE:
val = int(src1 != src2)
else:
elif op == IBNE:
val = int(src1 != src2)
else:
- return 0 # LD/ST TODO
+ return 0
# LD/ST TODO
val &= maxbits
self.setval(dest, val)
return val
def setval(self, dest, val):
val &= maxbits
self.setval(dest, val)
return val
def setval(self, dest, val):
- print
("sim setval", dest, hex(val))
+ print("sim setval", dest, hex(val))
self.regs[dest] = val
def dump(self, dut):
self.regs[dest] = val
def dump(self, dut):
@@
-81,4
+82,3
@@
class RegSim:
print("reg %d expected %x received %x\n" % (i, val, reg))
yield from self.dump(dut)
assert False
print("reg %d expected %x received %x\n" % (i, val, reg))
yield from self.dump(dut)
assert False
-