+ ###################
+ #### CMP, CMPL v3.0B p85-86
+
+ with m.Case(MicrOp.OP_CMP):
+ a_n = Signal(64) # temporary - inverted a
+ tval = Signal(5)
+ a_lt = Signal()
+ carry_32 = Signal()
+ carry_64 = Signal()
+ zerolo = Signal()
+ zerohi = Signal()
+ msb_a = Signal()
+ msb_b = Signal()
+ newcrf = Signal(4)
+
+ # this is supposed to be inverted (b-a, not a-b)
+ comb += a_n.eq(~a) # sigh a gets inverted
+ comb += carry_32.eq(add_o[33] ^ a[32] ^ b[32])
+ comb += carry_64.eq(add_o[65])
+
+ comb += zerolo.eq(~((a_n[0:32] ^ b[0:32]).bool()))
+ comb += zerohi.eq(~((a_n[32:64] ^ b[32:64]).bool()))
+
+ with m.If(zerolo & (is_32bit | zerohi)):
+ # values are equal
+ comb += tval[2].eq(1)
+ with m.Else():
+ comb += msb_a.eq(Mux(is_32bit, a_n[31], a_n[63]))
+ comb += msb_b.eq(Mux(is_32bit, b[31], b[63]))
+ C0 = Const(0, 1)
+ with m.If(msb_a != msb_b):
+ # Subtraction might overflow, but
+ # comparison is clear from MSB difference.
+ # for signed, 0 is greater; for unsigned, 1 is greater
+ comb += tval.eq(Cat(msb_a, msb_b, C0, msb_b, msb_a))
+ with m.Else():
+ # Subtraction cannot overflow since MSBs are equal.
+ # carry = 1 indicates RA is smaller (signed or unsigned)
+ comb += a_lt.eq(Mux(is_32bit, carry_32, carry_64))
+ comb += tval.eq(Cat(~a_lt, a_lt, C0, ~a_lt, a_lt))
+ comb += cr0.data[0:2].eq(Cat(xer_so_i[0], tval[2]))
+ with m.If(op.is_signed):
+ comb += cr0.data[2:4].eq(tval[3:5])
+ with m.Else():
+ comb += cr0.data[2:4].eq(tval[0:2])
+ comb += cr0.ok.eq(1)
+
+ ###################
+ #### add v3.0B p67, p69-72
+
+ with m.Case(MicrOp.OP_ADD):