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move common functionality between PipeSpecs to soc.fu.pipe_data
[soc.git]
/
src
/
soc
/
fu
/
branch
/
test
/
test_pipe_caller.py
diff --git
a/src/soc/fu/branch/test/test_pipe_caller.py
b/src/soc/fu/branch/test/test_pipe_caller.py
index 75cac8090f561b80d86defbccf3fc05c77353755..77bcdc0296d637fe235ed5f419e4883086f24a66 100644
(file)
--- a/
src/soc/fu/branch/test/test_pipe_caller.py
+++ b/
src/soc/fu/branch/test/test_pipe_caller.py
@@
-11,7
+11,6
@@
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
-
from soc.fu.branch.pipeline import BranchBasePipe
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
from soc.fu.branch.pipeline import BranchBasePipe
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
@@
-98,9
+97,7
@@
class BranchTestCase(FHDLTestCase):
initial_cr=cr)
def test_ilang(self):
initial_cr=cr)
def test_ilang(self):
- rec = BranchPipeSpec.opsubsetkls()
-
- pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = BranchPipeSpec(id_wid=2)
alu = BranchBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("branch_pipeline.il", "w") as f:
alu = BranchBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("branch_pipeline.il", "w") as f:
@@
-121,9
+118,7
@@
class TestRunner(FHDLTestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = BranchPipeSpec.opsubsetkls()
-
- pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = BranchPipeSpec(id_wid=2)
m.submodules.branch = branch = BranchBasePipe(pspec)
comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
m.submodules.branch = branch = BranchBasePipe(pspec)
comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)