- # XER.ca
- cry_out = yield dec2.e.output_carry
- if cry_out:
- expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- xer_ca = res['xer_ca']
- real_carry = xer_ca & 0b1 # XXX CO not CO32
- self.assertEqual(expected_carry, real_carry, code)
- expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
- real_carry32 = bool(xer_ca & 0b10) # XXX CO32
- self.assertEqual(expected_carry32, real_carry32, code)
+ ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
+ ALUHelpers.check_int_o(self, res, sim_o, code)