- yield alu.p.data_i.cr.eq(simulator.cr.get_range().value)
-
- reg3_ok = yield dec2.e.read_reg3.ok
- if reg3_ok:
- reg3_sel = yield dec2.e.read_reg3.data
- reg3 = simulator.gpr(reg3_sel).value
- yield alu.p.data_i.a.eq(reg3)
+ inp = yield from get_cu_inputs(dec2, simulator)
+ if 'full_cr' in inp:
+ yield alu.p.data_i.full_cr.eq(inp['full_cr'])
+ else:
+ yield alu.p.data_i.full_cr.eq(0)
+ if 'cr_a' in inp:
+ yield alu.p.data_i.cr_a.eq(inp['cr_a'])
+ if 'cr_b' in inp:
+ yield alu.p.data_i.cr_b.eq(inp['cr_b'])
+ if 'cr_c' in inp:
+ yield alu.p.data_i.cr_c.eq(inp['cr_c'])
+ if 'ra' in inp:
+ yield alu.p.data_i.ra.eq(inp['ra'])
+ else:
+ yield alu.p.data_i.ra.eq(0)
+ if 'rb' in inp:
+ yield alu.p.data_i.rb.eq(inp['rb'])
+ else:
+ yield alu.p.data_i.rb.eq(0)
+
+ def assert_outputs(self, alu, dec2, simulator, code):
+ whole_reg = yield dec2.e.write_cr_whole
+ cr_en = yield dec2.e.write_cr.ok
+ if whole_reg:
+ full_cr = yield alu.n.data_o.full_cr.data
+ expected_cr = simulator.cr.get_range().value
+ self.assertEqual(expected_cr, full_cr, code)
+ elif cr_en:
+ cr_sel = yield dec2.e.write_cr.data
+ expected_cr = simulator.crl[cr_sel].get_range().value
+ real_cr = yield alu.n.data_o.cr.data
+ self.assertEqual(expected_cr, real_cr, code)
+ alu_out = yield alu.n.data_o.o.data
+ out_reg_valid = yield dec2.e.write_reg.ok
+ if out_reg_valid:
+ write_reg_idx = yield dec2.e.write_reg.data
+ expected = simulator.gpr(write_reg_idx).value
+ print(f"expected {expected:x}, actual: {alu_out:x}")
+ self.assertEqual(expected, alu_out, code)