+ ]
+
+
+class LogicalOutputData(IntegerData):
+ regspec = [('INT', 'o', '0:63'),
+ ('CR', 'cr0', '0:3'),
+ ('XER', 'xer_ca', '34,45'),
+ ]
+ def __init__(self, pspec):
+ super().__init__(pspec)
+ self.o = Data(64, name="stage_o") # RT
+ self.cr0 = Data(4, name="cr0")
+ self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
+
+ def __iter__(self):
+ yield from super().__iter__()
+ yield self.o
+ yield self.xer_ca
+ yield self.cr0
+
+ def eq(self, i):
+ lst = super().eq(i)
+ return lst + [self.o.eq(i.o),