-from openpower.decoder.power_enums import MicrOp, XER_bits
-
-from soc.experiment.pimem import PortInterface
-from soc.experiment.pimem import PortInterfaceBase
-
-from soc.experiment.mem_types import LoadStore1ToDCacheType, LoadStore1ToMMUType
-from soc.experiment.mem_types import DCacheToLoadStore1Type, MMUToLoadStore1Type
-
-from soc.minerva.wishbone import make_wb_layout
-from soc.bus.sram import SRAM
-
-
-# glue logic for microwatt mmu and dcache
-class LoadStore1(PortInterfaceBase):
- def __init__(self, pspec):
- self.pspec = pspec
- regwid = pspec.reg_wid
- addrwid = pspec.addr_wid
-
- super().__init__(regwid, addrwid)
- self.dcache = DCache()
- self.d_in = self.dcache.d_in
- self.d_out = self.dcache.d_out
- self.l_in = LoadStore1ToMMUType()
- self.l_out = MMUToLoadStore1Type()
- # for debugging with gtkwave only
- self.debug1 = Signal()
- self.debug2 = Signal()
- # TODO microwatt
- self.mmureq = Signal()
- self.derror = Signal()
-
- # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
- self.dbus = Record(make_wb_layout(pspec))
-
- def set_wr_addr(self, m, addr, mask):
- #m.d.comb += self.d_in.valid.eq(1)
- #m.d.comb += self.l_in.valid.eq(1)
- #m.d.comb += self.d_in.load.eq(0)
- #m.d.comb += self.l_in.load.eq(0)
- # set phys addr on both units
- m.d.comb += self.d_in.addr.eq(addr)
- m.d.comb += self.l_in.addr.eq(addr)
- # TODO set mask
- return None
-
- def set_rd_addr(self, m, addr, mask):
- m.d.comb += self.d_in.valid.eq(1)
- m.d.comb += self.l_in.valid.eq(1)
- m.d.comb += self.d_in.load.eq(1)
- m.d.comb += self.l_in.load.eq(1)
- m.d.comb += self.d_in.addr.eq(addr)
- m.d.comb += self.l_in.addr.eq(addr)
- m.d.comb += self.debug1.eq(1)
- # m.d.comb += self.debug2.eq(1)
- return None #FIXME return value
-
- def set_wr_data(self, m, data, wen):
- m.d.comb += self.d_in.data.eq(data)
- # TODO set wen
- st_ok = Const(1, 1)
- return st_ok
-
- def get_rd_data(self, m):
- ld_ok = self.d_out.valid # indicates read data is valid
- data = self.d_out.data # actual read data
- return data, ld_ok
-
- """
- if d_in.error = '1' then
- if d_in.cache_paradox = '1' then
- -- signal an interrupt straight away
- exception := '1';
- dsisr(63 - 38) := not r2.req.load;
- -- XXX there is no architected bit for this
- -- (probably should be a machine check in fact)
- dsisr(63 - 35) := d_in.cache_paradox;
- else
- -- Look up the translation for TLB miss
- -- and also for permission error and RC error
- -- in case the PTE has been updated.
- mmureq := '1';
- v.state := MMU_LOOKUP;
- v.stage1_en := '0';
- end if;
- end if;
- """
-
- def elaborate(self, platform):
- m = super().elaborate(platform)
- comb = m.d.comb
-
- # create dcache module
- m.submodules.dcache = dcache = self.dcache
-
- # temp vars
- d_out, l_out, dbus = self.d_out, self.l_out, self.dbus
-
- with m.If(d_out.error):
- with m.If(d_out.cache_paradox):
- comb += self.derror.eq(1)
- # dsisr(63 - 38) := not r2.req.load;
- # -- XXX there is no architected bit for this
- # -- (probably should be a machine check in fact)
- # dsisr(63 - 35) := d_in.cache_paradox;
- with m.Else():
- # Look up the translation for TLB miss
- # and also for permission error and RC error
- # in case the PTE has been updated.
- comb += self.mmureq.eq(1)
- # v.state := MMU_LOOKUP;
- # v.stage1_en := '0';
-
- exc = self.pi.exception_o
-
- #happened, alignment, instr_fault, invalid,
- comb += exc.happened.eq(d_out.error | l_out.err)
- comb += exc.invalid.eq(l_out.invalid)
-
- #badtree, perm_error, rc_error, segment_fault
- comb += exc.badtree.eq(l_out.badtree)
- comb += exc.perm_error.eq(l_out.perm_error)
- comb += exc.rc_error.eq(l_out.rc_error)
- comb += exc.segment_fault.eq(l_out.segerr)
-
- # TODO connect those signals somewhere
- #print(d_out.valid) -> no error
- #print(d_out.store_done) -> no error
- #print(d_out.cache_paradox) -> ?
- #print(l_out.done) -> no error
-
- # TODO some exceptions set SPRs
-
- # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
- comb += dbus.adr.eq(dcache.wb_out.adr)
- comb += dbus.dat_w.eq(dcache.wb_out.dat)
- comb += dbus.sel.eq(dcache.wb_out.sel)
- comb += dbus.cyc.eq(dcache.wb_out.cyc)
- comb += dbus.stb.eq(dcache.wb_out.stb)
- comb += dbus.we.eq(dcache.wb_out.we)
-
- comb += dcache.wb_in.dat.eq(dbus.dat_r)
- comb += dcache.wb_in.ack.eq(dbus.ack)
- if hasattr(dbus, "stall"):
- comb += dcache.wb_in.stall.eq(dbus.stall)
-
- return m
-
- def ports(self):
- yield from super().ports()
- # TODO: memory ports