+ # take a copy of the current SVSTATE into SVSRR0
+ comb += svsrr0_o.data.eq(svstate_i) # old SVSTATE
+ comb += svsrr0_o.ok.eq(1)
+
+ def msr_exception(self, m, trap_addr, msr_hv=None):
+ """msr_exception - sets bits in MSR specific to an exception.
+ the full list of what needs to be done is given in V3.0B
+ Book III Section 6.5 p1063 however it turns out that for the
+ majority of cases (microwatt showing the way, here), all these
+ bits are all set by all (implemented) interrupt types. this
+ may change in the future, hence the (unused) trap_addr argument
+ """
+ comb = m.d.comb
+ op = self.i.ctx.op
+ msr_i, msr_o = op.msr, self.o.msr
+ comb += msr_o.data.eq(msr_i) # copy msr, first, then modify
+ comb += msr_o.data[MSR.SF].eq(1)
+ comb += msr_o.data[MSR.EE].eq(0)
+ comb += msr_o.data[MSR.PR].eq(0)
+ comb += msr_o.data[MSR.IR].eq(0)
+ comb += msr_o.data[MSR.DR].eq(0)
+ comb += msr_o.data[MSR.RI].eq(0)
+ comb += msr_o.data[MSR.LE].eq(1)
+ comb += msr_o.data[MSR.FE0].eq(0)
+ comb += msr_o.data[MSR.FE1].eq(0)
+ comb += msr_o.data[MSR.VSX].eq(0)
+ comb += msr_o.data[MSR.TM].eq(0)
+ comb += msr_o.data[MSR.VEC].eq(0)
+ comb += msr_o.data[MSR.FP].eq(0)
+ comb += msr_o.data[MSR.PMM].eq(0)
+ comb += msr_o.data[MSR.TEs].eq(0) # this is only 2 bits
+ comb += msr_o.data[MSR.TEe].eq(0) # so just zero them both
+ comb += msr_o.data[MSR.UND].eq(0)
+ if msr_hv is not None:
+ comb += msr_o.data[MSR.HV].eq(msr_hv)
+ comb += msr_o.ok.eq(1)
+