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bit of a reorg of mul proof, tracking down missing
[soc.git]
/
src
/
soc
/
fu
/
trap
/
trap_input_record.py
diff --git
a/src/soc/fu/trap/trap_input_record.py
b/src/soc/fu/trap/trap_input_record.py
index 111368caf205b5489b0b4ca01341ee725707c540..dd87f30ffa6f2bab85b1e957ebd6efba15e5fbec 100644
(file)
--- a/
src/soc/fu/trap/trap_input_record.py
+++ b/
src/soc/fu/trap/trap_input_record.py
@@
-1,5
+1,6
@@
from soc.fu.base_input_record import CompOpSubsetBase
from soc.decoder.power_enums import (MicrOp, Function)
from soc.fu.base_input_record import CompOpSubsetBase
from soc.decoder.power_enums import (MicrOp, Function)
+from soc.consts import TT
class CompTrapOpSubset(CompOpSubsetBase):
class CompTrapOpSubset(CompOpSubsetBase):
@@
-13,8
+14,10
@@
class CompTrapOpSubset(CompOpSubsetBase):
layout = (('insn_type', MicrOp),
('fn_unit', Function),
('insn', 32),
layout = (('insn_type', MicrOp),
('fn_unit', Function),
('insn', 32),
+ ('msr', 64), # TODO: "state" in separate Record
+ ('cia', 64), # likewise
('is_32bit', 1),
('is_32bit', 1),
- ('traptype',
5), # see trap main_stage.py and
PowerDecoder2
+ ('traptype',
TT.size), # see trap main_stage.py,
PowerDecoder2
('trapaddr', 13),
)
('trapaddr', 13),
)