+from openpower.decoder.power_enums import SPRfull, SPRreduced
+
+# XXX MAKE DAMN SURE TO KEEP THESE UP-TO-DATE if changing/adding regs
+from openpower.consts import StateRegsEnum, XERRegsEnum, FastRegsEnum
+
+from nmigen import Module
+from nmigen.cli import rtlil
+from nmutil.latch import SRLatch
+
+
+def create_ports(rf, wr_spec, rd_spec):
+ """create_ports: creates register file ports based on requested specs
+ """
+ rf.r_ports, rf.w_ports = {}, {}
+ # create read ports based on read specs
+ for key, name in rd_spec.items():
+ if hasattr(rf, name): # some regfiles already have a port
+ rf.r_ports[key] = getattr(rf, name)
+ else:
+ rf.r_ports[key] = rf.read_port(name)
+ # create write ports based on write specs
+ for key, name in wr_spec.items():
+ if hasattr(rf, name): # some regfiles already have a port
+ rf.w_ports[key] = getattr(rf, name)
+ else:
+ rf.w_ports[key] = rf.write_port(name)