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connect up DEC/TB FSM pauser from core to Issuer
[soc.git]
/
src
/
soc
/
simple
/
issuer.py
diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index e11f3d35d53f7ef5b76136ee81f0d47b76b222c3..ab21b1b95c26250f8dfc0ded8c5d98aa18ca7847 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-396,6
+396,10
@@
class TestIssuerBase(Elaboratable):
m.submodules["sram4k_%d" % i] = csd(sram)
comb += sram.enable.eq(self.wb_sram_en)
m.submodules["sram4k_%d" % i] = csd(sram)
comb += sram.enable.eq(self.wb_sram_en)
+ # terrible hack to stop a potential race condition. if core
+ # is doing any operation (at all) pause the DEC/TB FSM
+ comb += self.pause_dec_tb.eq(core.pause_dec_tb)
+
# XICS interrupt handler
if self.xics:
m.submodules.xics_icp = icp = csd(self.xics_icp)
# XICS interrupt handler
if self.xics:
m.submodules.xics_icp = icp = csd(self.xics_icp)