+class TestIssuer(Elaboratable):
+ def __init__(self, pspec):
+ self.ti = TestIssuerInternal(pspec)
+
+ self.pll = DummyPLL()
+ self.clksel = ClockSelect()
+
+ # PLL direct clock or not
+ self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+
+ # TestIssuer runs at direct clock
+ m.submodules.ti = ti = self.ti
+ cd_int = ClockDomain("coresync")
+
+ # ClockSelect runs at PLL output internal clock rate
+ m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
+ m.submodules.pll = pll = self.pll
+
+ # add 2 clock domains established above...
+ cd_pll = ClockDomain("pllclk")
+ m.domains += cd_pll
+
+ # internal clock is set to selector clock-out. has the side-effect of
+ # running TestIssuer at this speed (see DomainRenamer("intclk") above)
+ intclk = ClockSignal("coresync")
+ if self.pll_en:
+ comb += intclk.eq(clksel.core_clk_o)
+ else:
+ comb += intclk.eq(ClockSignal())
+
+ # PLL clock established. has the side-effect of running clklsel
+ # at the PLL's speed (see DomainRenamer("pllclk") above)
+ pllclk = ClockSignal("pllclk")
+ comb += pllclk.eq(pll.clk_pll_o)
+
+ # wire up external 24mhz to PLL and clksel
+ comb += clksel.clk_24_i.eq(ClockSignal())
+ comb += pll.clk_24_i.eq(clksel.clk_24_i)
+
+ # now wire up ResetSignals. don't mind them all being in this domain
+ #int_rst = ResetSignal("coresync")
+ pll_rst = ResetSignal("pllclk")
+ #comb += int_rst.eq(ResetSignal())
+ comb += pll_rst.eq(ResetSignal())
+
+ return m
+
+ def ports(self):
+ return list(self.ti.ports()) + list(self.pll.ports()) + \
+ [ClockSignal(), ResetSignal()] + \
+ list(self.clksel.ports())
+
+ def external_ports(self):
+ ports = self.ti.external_ports()
+ ports.append(ClockSignal())
+ ports.append(ResetSignal())
+ ports.append(self.clksel.clk_sel_i)
+ ports.append(self.clksel.pll_48_o)
+ return ports
+
+