+ # set RA_OR_ZERO detection in satellite decoders
+ sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
+ # loop into ISSUE_START if it's a SVP64 instruction
+ # and VL == 0. this because VL==0 is a for-loop
+ # from 0 to 0 i.e. always, always a NOP.
+ cur_vl = cur_state.svstate.vl
+ with m.If(is_svp64_mode & (cur_vl == 0)):
+ # update the PC before fetching the next instruction
+ # since we are in a VL==0 loop, no instruction was
+ # executed that we could be overwriting
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.data_i.eq(nia)
+ comb += self.insn_done.eq(1)
+ m.next = "ISSUE_START"
+ with m.Else():
+ m.next = "INSN_EXECUTE" # move to "execute"
+
+ # handshake with execution FSM, move to "wait" once acknowledged
+ with m.State("INSN_EXECUTE"):
+ comb += exec_insn_valid_i.eq(1) # trigger execute
+ with m.If(exec_insn_ready_o): # execute acknowledged us
+ m.next = "EXECUTE_WAIT"
+
+ with m.State("EXECUTE_WAIT"):
+ # wait on "core stop" release, at instruction end
+ # need to do this here, in case we are in a VL>1 loop
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ comb += exec_pc_ready_i.eq(1)
+ with m.If(exec_pc_valid_o):
+ # precalculate srcstep+1 and dststep+1
+ # TODO these need to "skip" over predicated-out src/dst
+ # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
+ # but still without exceeding VL in either case
+ next_srcstep = Signal.like(cur_state.svstate.srcstep)
+ next_dststep = Signal.like(cur_state.svstate.dststep)
+ comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
+ comb += next_dststep.eq(cur_state.svstate.dststep+1)
+
+ # was this the last loop iteration?
+ is_last = Signal()
+ cur_vl = cur_state.svstate.vl
+ comb += is_last.eq(next_srcstep == cur_vl)
+
+ # if either PC or SVSTATE were changed by the previous
+ # instruction, go directly back to Fetch, without
+ # updating either PC or SVSTATE
+ with m.If(pc_changed | sv_changed):
+ m.next = "ISSUE_START"
+
+ # also return to Fetch, when no output was a vector
+ # (regardless of SRCSTEP and VL), or when the last
+ # instruction was really the last one of the VL loop
+ with m.Elif((~pdecode2.loop_continue) | is_last):
+ # before going back to fetch, update the PC state
+ # register with the NIA.
+ # ok here we are not reading the branch unit.
+ # TODO: this just blithely overwrites whatever
+ # pipeline updated the PC
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.data_i.eq(nia)
+ # reset SRCSTEP before returning to Fetch
+ with m.If(pdecode2.loop_continue):
+ comb += new_svstate.srcstep.eq(0)
+ comb += new_svstate.dststep.eq(0)
+ comb += update_svstate.eq(1)
+ m.next = "ISSUE_START"
+
+ # returning to Execute? then, first update SRCSTEP
+ with m.Else():
+ comb += new_svstate.srcstep.eq(next_srcstep)
+ comb += new_svstate.dststep.eq(next_dststep)
+ comb += update_svstate.eq(1)
+ m.next = "DECODE_SV"
+
+ with m.Else():
+ comb += core.core_stopped_i.eq(1)
+ comb += dbg.core_stopped_i.eq(1)
+ # while stopped, allow updating the PC and SVSTATE
+ with m.If(self.pc_i.ok):
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+ sync += pc_changed.eq(1)
+ with m.If(self.svstate_i.ok):
+ comb += new_svstate.eq(self.svstate_i.data)
+ comb += update_svstate.eq(1)
+ sync += sv_changed.eq(1)
+
+ # need to decode the instruction again, after updating SRCSTEP
+ # in the previous state.
+ # mostly a copy of INSN_WAIT, but without the actual wait
+ with m.State("DECODE_SV"):
+ # decode the instruction
+ sync += core.e.eq(pdecode2.e)
+ sync += core.state.eq(cur_state)
+ sync += core.bigendian_i.eq(self.core_bigendian_i)
+ sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
+ m.next = "INSN_EXECUTE" # move to "execute"
+
+ # check if svstate needs updating: if so, write it to State Regfile
+ with m.If(update_svstate):
+ comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
+ comb += self.state_w_sv.data_i.eq(new_svstate)
+ sync += cur_state.svstate.eq(new_svstate) # for next clock
+
+ def execute_fsm(self, m, core, pc_changed, sv_changed,
+ exec_insn_valid_i, exec_insn_ready_o,
+ exec_pc_valid_o, exec_pc_ready_i):
+ """execute FSM
+
+ execute FSM. this interacts with the "issue" FSM
+ through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
+ (outgoing). SVP64 RM prefixes have already been set up by the
+ "issue" phase, so execute is fairly straightforward.
+ """
+
+ comb = m.d.comb
+ sync = m.d.sync
+ pdecode2 = self.pdecode2
+
+ # temporaries
+ core_busy_o = core.busy_o # core is busy
+ core_ivalid_i = core.ivalid_i # instruction is valid
+ core_issue_i = core.issue_i # instruction is issued
+ insn_type = core.e.do.insn_type # instruction MicroOp type
+
+ with m.FSM(name="exec_fsm"):