+from soc.fu.branch.test.test_pipe_caller import BranchTestCase
+from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
+from soc.regfile.util import spr_to_fast_reg
+
+
+def setup_regs(core, test):
+
+ # set up INT regfile, "direct" write (bypass rd/write ports)
+ intregs = core.regs.int
+ for i in range(32):
+ yield intregs.regs[i].reg.eq(test.regs[i])
+
+ # set up CR regfile, "direct" write across all CRs
+ cr = test.cr
+ crregs = core.regs.cr
+ #cr = int('{:32b}'.format(cr)[::-1], 2)
+ print("cr reg", hex(cr))
+ for i in range(8):
+ #j = 7-i
+ cri = (cr >> (i*4)) & 0xf
+ #cri = int('{:04b}'.format(cri)[::-1], 2)
+ print("cr reg", hex(cri), i,
+ crregs.regs[i].reg.shape())
+ yield crregs.regs[i].reg.eq(cri)
+
+ # set up XER. "direct" write (bypass rd/write ports)
+ xregs = core.regs.xer
+ print("sprs", test.sprs)
+ xer = None
+ if 'XER' in test.sprs:
+ xer = test.sprs['XER']
+ if 1 in test.sprs:
+ xer = test.sprs[1]
+ if xer is not None:
+ if isinstance(xer, int):
+ xer = SelectableInt(xer, 64)
+ sobit = xer[XER_bits['SO']].value
+ yield xregs.regs[xregs.SO].reg.eq(sobit)
+ cabit = xer[XER_bits['CA']].value
+ ca32bit = xer[XER_bits['CA32']].value
+ yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
+ ovbit = xer[XER_bits['OV']].value
+ ov32bit = xer[XER_bits['OV32']].value
+ yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
+ print("setting XER so %d ca %d ca32 %d ov %d ov32 %d" %
+ (sobit, cabit, ca32bit, ovbit, ov32bit))
+ else:
+ yield xregs.regs[xregs.SO].reg.eq(0)
+ yield xregs.regs[xregs.OV].reg.eq(0)
+ yield xregs.regs[xregs.CA].reg.eq(0)
+
+ # setting both fast and slow SPRs from test data
+
+ fregs = core.regs.fast
+ sregs = core.regs.spr
+ for sprname, val in test.sprs.items():
+ if isinstance(val, SelectableInt):
+ val = val.value
+ if isinstance(sprname, int):
+ sprname = spr_dict[sprname].SPR
+ if sprname == 'XER':
+ continue
+ fast = spr_to_fast_reg(sprname)
+ if fast is None:
+ # match behaviour of SPRMap in power_decoder2.py
+ for i, x in enumerate(SPR):
+ if sprname == x.name:
+ yield sregs[i].reg.eq(val)
+ print("setting slow SPR %d (%s) to %x" %
+ (i, sprname, val))
+ else:
+ yield fregs.regs[fast].reg.eq(val)
+ print("setting fast reg %d (%s) to %x" %
+ (fast, sprname, val))
+
+ # allow changes to settle before reporting on XER
+ yield Settle()