-from soc.fu.alu.test.test_pipe_caller import ALUTestCase
-from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
-from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
-from soc.fu.cr.test.test_pipe_caller import CRTestCase
-from soc.fu.branch.test.test_pipe_caller import BranchTestCase
-from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
-from soc.simulator.test_sim import GeneralTestCases
-
-
-def setup_i_memory(imem, startaddr, instructions):
- mem = imem
- print ("insn before, init mem", mem.depth, mem.width, mem)
- for i in range(mem.depth):
- yield mem._array[i].eq(0)
- yield Settle()
- startaddr //= 4 # instructions are 32-bit
- mask = ((1<<64)-1)
- for insn, code in instructions:
- msbs = (startaddr>>1) & mask
- val = yield mem._array[msbs]
- print ("before set", hex(startaddr), hex(msbs), hex(val))
- lsb = 1 if (startaddr & 1) else 0
- val = (val | (insn << (lsb*32))) & mask
- yield mem._array[msbs].eq(val)
- yield Settle()
- print ("after set", hex(startaddr), hex(msbs), hex(val))
- print ("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
- startaddr += 1
- startaddr = startaddr & mask
-
-
-class TestRunner(FHDLTestCase):
- def __init__(self, tst_data):
- super().__init__("run_all")
- self.test_data = tst_data
-
- def run_all(self):
- m = Module()
- comb = m.d.comb
- go_insn_i = Signal()
- pc_i = Signal(32)
-
- pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
- imem_ifacetype='test_bare_wb',
- addr_wid=48,
- mask_wid=8,
- reg_wid=64)
- m.submodules.issuer = issuer = TestIssuer(pspec)
- imem = issuer.imem._get_memory()
- core = issuer.core
- pdecode2 = core.pdecode2
- l0 = core.l0
-
- comb += issuer.pc_i.data.eq(pc_i)
- comb += issuer.go_insn_i.eq(go_insn_i)
-
- # nmigen Simulation
- sim = Simulator(m)
- sim.add_clock(1e-6)
-
- def process():
-
- for test in self.test_data:
- print(test.name)
- program = test.program
- self.subTest(test.name)
- print ("regs", test.regs)
- print ("sprs", test.sprs)
- print ("cr", test.cr)
- print ("mem", test.mem)
- print ("msr", test.msr)
- print ("assem", program.assembly)
- gen = list(program.generate_instructions())
- insncode = program.assembly.splitlines()
- instructions = list(zip(gen, insncode))
- sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
- test.msr,
- initial_insns=gen, respect_pc=True,
- disassembly=insncode)
+from openpower.test.alu.alu_cases import ALUTestCase
+from openpower.test.div.div_cases import DivTestCases
+from openpower.test.logical.logical_cases import LogicalTestCase
+from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase
+from openpower.test.cr.cr_cases import CRTestCase
+# from soc.fu.branch.test.test_pipe_caller import BranchTestCase
+# from soc.fu.spr.test.test_pipe_caller import SPRTestCase
+from openpower.test.ldst.ldst_cases import LDSTTestCase
+from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
+# from openpower.simulator.test_helloworld_sim import HelloTestCases