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radix: reading first page table entry
[soc.git]
/
src
/
soc
/
simulator
/
test_mul_sim.py
diff --git
a/src/soc/simulator/test_mul_sim.py
b/src/soc/simulator/test_mul_sim.py
index 7c24fa669db8155911dd274ccbb1e9be1e62e193..6d251056aeb34041927ec1f7773935627e894382 100644
(file)
--- a/
src/soc/simulator/test_mul_sim.py
+++ b/
src/soc/simulator/test_mul_sim.py
@@
-1,9
+1,9
@@
from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nm
igen.test.utils
import FHDLTestCase
+from nm
util.formaltest
import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function,
Internal
Op,
+from soc.decoder.power_enums import (Function,
Micr
Op,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
@@
-14,6
+14,7
@@
from soc.simulator.qemu import run_program
from soc.decoder.isa.all import ISA
from soc.fu.test.common import TestCase
from soc.simulator.test_sim import DecoderBase
from soc.decoder.isa.all import ISA
from soc.fu.test.common import TestCase
from soc.simulator.test_sim import DecoderBase
+from soc.config.endian import bigendian
@@
-28,15
+29,15
@@
class MulTestCases(FHDLTestCase):
lst = ["addi 1, 0, 0x5678",
"addi 2, 0, 0x1234",
"mullw 3, 1, 2"]
lst = ["addi 1, 0, 0x5678",
"addi 2, 0, 0x1234",
"mullw 3, 1, 2"]
- self.run_tst_program(Program(lst), [3])
+ self.run_tst_program(Program(lst
, bigendian
), [3])
- def test_mullwo
_
(self):
+ def test_mullwo(self):
lst = ["addi 1, 0, 0x5678",
"neg 1, 1",
"addi 2, 0, 0x1234",
"neg 2, 2",
"mullwo 3, 1, 2"]
lst = ["addi 1, 0, 0x5678",
"neg 1, 1",
"addi 2, 0, 0x1234",
"neg 2, 2",
"mullwo 3, 1, 2"]
- self.run_tst_program(Program(lst), [3])
+ self.run_tst_program(Program(lst
, bigendian
), [3])
def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
initial_mem=None):
def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
initial_mem=None):