+ @unittest.skip("disable")
+ def test_add_with_carry(self):
+ lst = ["addi 1, 0, 5",
+ "neg 1, 1",
+ "addi 2, 0, 7",
+ "neg 2, 2",
+ "addc 3, 2, 1",
+ "addi 3, 3, 1"
+ ]
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [1, 2, 3])
+
+ @unittest.skip("disable")
+ def test_addis(self):
+ lst = ["addi 1, 0, 0x0FFF",
+ "addis 1, 1, 0x0F"
+ ]
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [1])
+
+ @unittest.skip("broken")
+ def test_mulli(self):
+ lst = ["addi 1, 0, 3",
+ "mulli 1, 1, 2"
+ ]
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [1])
+
+ @unittest.skip("disable")
+ def test_2_load_store(self):
+ lst = ["addi 1, 0, 0x1004",
+ "addi 2, 0, 0x1008",
+ "addi 3, 0, 0x00ee",
+ "stb 3, 1(2)",
+ "lbz 4, 1(2)",
+ ]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1004
+ initial_regs[2] = 0x1008
+ initial_regs[3] = 0x00ee
+ initial_mem = {0x1000: (0x5432123412345678, 8),
+ 0x1008: (0xabcdef0187654321, 8),
+ 0x1020: (0x1828384822324252, 8),
+ }
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [3,4], initial_mem)
+
+ @unittest.skip("disable")
+ def test_3_load_store(self):
+ lst = ["addi 1, 0, 0x1004",
+ "addi 2, 0, 0x1002",
+ "addi 3, 0, 0x15eb",
+ "sth 4, 0(2)",
+ "lhz 4, 0(2)"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1004
+ initial_regs[2] = 0x1002
+ initial_regs[3] = 0x15eb
+ initial_mem = {0x1000: (0x5432123412345678, 8),
+ 0x1008: (0xabcdef0187654321, 8),
+ 0x1020: (0x1828384822324252, 8),
+ }
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [1,2,3,4], initial_mem)
+
+ def test_loop(self):
+ """in godbolt.org:
+ register unsigned long i asm ("r12");
+ void square(void) {
+ i = 5;
+ do {
+ i = i - 1;
+ } while (i != 0);
+ }
+ """
+ lst = ["addi 9, 0, 0x10", # i = 16
+ "addi 9,9,-1", # i = i - 1
+ "cmpi 0,1,9,12", # compare 9 to value 0, store in CR2
+ "bc 4,0,-8" # branch if CR2 "test was != 0"
+ ]
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [9], initial_mem={})
+
+ def test_30_addis(self):
+ lst = [#"addi 0, 0, 5",
+ "addis 12, 0, 0",
+ ]
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [12])
+
+ def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
+ initial_mem=None):
+ initial_regs = [0] * 32
+ tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
+ initial_mem, 0)
+ self.test_data.append(tc)
+
+
+class DecoderBase:
+
+ def run_tst(self, generator, initial_mem=None, initial_pc=0):
+ m = Module()
+ comb = m.d.comb
+
+ gen = list(generator.generate_instructions())
+ insn_code = generator.assembly.splitlines()
+ instructions = list(zip(gen, insn_code))
+
+ pdecode = create_pdecode()
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+
+ # place program at requested address
+ gen = (initial_pc, gen)
+
+ simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0,
+ initial_insns=gen, respect_pc=True,
+ disassembly=insn_code,
+ initial_pc=initial_pc,
+ bigendian=bigendian)
+
+ sim = Simulator(m)
+
+ def process():
+ #yield pdecode2.dec.bigendian.eq(bigendian)
+ yield Settle()
+
+ while True:
+ try:
+ yield from simulator.setup_one()
+ except KeyError: # indicates instruction not in imem: stop
+ break
+ yield Settle()
+ yield from simulator.execute_one()
+ yield Settle()
+
+
+ sim.add_process(process)
+ with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+ traces=[]):
+ sim.run()
+
+ return simulator
+
+ def run_tst_program(self, prog, reglist, initial_mem=None,
+ extra_break_addr=None):
+ import sys
+ simulator = self.run_tst(prog, initial_mem=initial_mem,
+ initial_pc=0x20000000)