cp pinmux/ls180/ls180_pins.py src/soc/debug
cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
-install: gitupdate develop mkpinmux svanalysis
+install: gitupdate develop mkpinmux
+# this is now actually part of openpower-isa repository
pywriter:
- python3 src/soc/decoder/pseudo/pywriter.py
+ echo "pywriter is part of openpower-isa, run that instead"
+# this is now actually part of openpower-isa repository
svanalysis:
- python3 libreriscv/openpower/sv_analysis.py
+ echo "sv_analysis is part of openpower-isa, run that instead"
develop:
python3 setup.py develop # yes, develop, not install
--enable-xics --enable-sram4x4kblock --disable-svp64 \
src/soc/litex/florent/libresoc/libresoc.v
+# build microwatt "external core", note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+ external_core_top.v
+
+# build microwatt "external core" with fixed 64-bit width SVP64
+# note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core_svp64:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat-svp64 --enable-mmu \
+ external_core_top.v
+
+microwatt_external_core_spi:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --small-cache \
+ --enable-mmu \
+ --pc-reset 0x10000000 \
+ external_core_top.v
+
+# microwatt-compatible core with smaller cache size (quick. VERSA_ECP5. just)
+microwatt_external_core_bram:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --small-cache \
+ --enable-mmu \
+ --pc-reset 0xFF000000 \
+ external_core_top.v
+
+# microwatt-compatible core with larger cache size (experiment on arty)
+microwatt_external_core_bram_arty:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --enable-mmu \
+ --pc-reset 0xFF000000 \
+ external_core_top.v
+
# build the litex libresoc SoC without 4k SRAMs
ls180_verilog_build: ls180_verilog
make -C soc/soc/litex/florent ls180