-YOSYS_TOP=/tmp/yosys_top
-LIBERTY_FILE=/path/to/alliance-check-toolkit/cells/nsxlib/nsxlib.lib
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
-include mk/synthesis-yosys.mk
+ LOGICAL_SYNTHESIS = Yosys
+ PHYSICAL_SYNTHESIS = Coriolis
+ DESIGN_KIT = sxlib
-top.blif: top.il
+# YOSYS_FLATTEN = Yes
+ USE_CLOCKTREE = Yes
+ USE_DEBUG = No
+ USE_KITE = No
-clean:
- rm *.blif
- rm *.tcl
+ NETLISTS = $(shell cat nets.txt)
+
+
+ include ./mk/design-flow.mk
+
+
+blif: part_sig_add.blif
+vst: part_sig_add.vst
+layout: part_sig_add_cts_r.ap
+gds: part_sig_add_cts_r.gds
+
+lvx: lvx-part_sig_add_cts_r
+druc: druc-part_sig_add_cts_r
+view: cgt-part_sig_add_cts_r