Make the VL loop reentrant in HDL

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index b7d73ee58c280d298136d9773db7bffa972747c9..8412997a74c3d17be68fc35c703947a8119dc367 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -36,6 +36,12 @@ testgpio_run_sim:
        python3 src/soc/litex/florent/sim.py --cpu=libresoc \
                        --variant=standardjtagtestgpio
 
+ls180_verilog_nopll:
+       python3 src/soc/simple/issuer_verilog.py \
+               --debug=jtag --enable-core --disable-pll \
+               --enable-xics --disable-svp64 \
+                       src/soc/litex/florent/libresoc/libresoc.v
+
 ls180_verilog:
        python3 src/soc/simple/issuer_verilog.py \
                --debug=jtag --enable-core --enable-pll \
@@ -49,8 +55,8 @@ ls180_4k_verilog:
                        src/soc/litex/florent/libresoc/libresoc.v
 
 # build the litex libresoc SoC without 4k SRAMs
-ls180_4ksram_verilog_build: ls180_verilog
-       make -C soc/soc/litex/florent ls1804k
+ls180_verilog_build: ls180_verilog
+       make -C soc/soc/litex/florent ls180
 
 # build the litex libresoc SoC with 4k SRAMs
 ls180_4ksram_verilog_build: ls180_4k_verilog