Add valid bit check to permission validator

[soc.git] / TLB / src / PermissionValidator.py

diff --git a/TLB/src/PermissionValidator.py b/TLB/src/PermissionValidator.py
index dc7ae88fc4526f9559813ca93e6a436a2db70c96..c948391477463af70c085b22c9ab3766ab66bfaa 100644 (file)
--- a/TLB/src/PermissionValidator.py
+++ b/TLB/src/PermissionValidator.py
@@ -1,4 +1,4 @@
-from nmigen import Signal
+from nmigen import Module, Signal
 from nmigen.cli import main
 
 class PermissionValidator():
@@ -15,50 +15,43 @@ class PermissionValidator():
             * data_size: (bit count) The size of the data words being processed
 
             Return:
-            1. Data is valid ->  valid is HIGH
-            2. Data is not valid -> valid is LOW
+            * valid HIGH when permissions are correct
         """
         # Input
         self.data = Signal(data_size);
         self.xwr = Signal(3) # Execute, Write, Read
-        self.super = Signal(1) # Supervisor Mode
+        self.super_mode = Signal(1) # Supervisor Mode
         self.super_access = Signal(1) # Supervisor Access
         self.asid = Signal(15) # Address Space IDentifier (ASID)
 
         # Output
         self.valid = Signal(1) # Denotes if the permissions are correct
 
-    def elaborate(self, platform):
+    def elaborate(self, platform=None):
         m = Module()
-        m.d.comb += [
-            # Check if ASID matches OR entry is global
-            If(data[64:78] == self.asid or data[5] == 1,
-               # Check Execute, Write, Read (XWR) Permissions
-               If(data[3] == self.xwr[2] and data[2] == self.xwr[1] \
-                  and data[1] == self.xwr[0],
-                  # Check if supervisor
-                  If(self.super == 1,
-                     # Check if entry is in user mode
-                     # Check if supervisor has access
-                     If(data[4] == 0,
-                        self.valid.eq(1)
-                     ).Elif(self.super_access == 1,
-                        self.valid.eq(1)
-                     ).Else(
-                        self.valid.eq(0)
-                     )
-                  ).Else(
-                      # Check if entry is in user mode
-                      If(data[4] == 1,
-                         self.valid.eq(1)
-                      ).Else(
-                         self.valid.eq(0)
-                      )
-                  )
-               ).Else(
-                   self.valid.eq(0)
-               )
-            ).Else(
-                self.valid.eq(0)
-            )
-        ]
+        # Check if the entry is valid
+        with m.If(self.data[0]):
+            # ASID match or Global Permission
+            # Note that the MSB bound is exclusive
+            with m.If((self.data[64:79] == self.asid) | self.data[5]):
+                # Check Execute, Write, Read (XWR) Permissions
+                with m.If((self.data[3] == self.xwr[2]) \
+                          & (self.data[2] == self.xwr[1]) \
+                          & (self.data[1] == self.xwr[0])):
+                    # Supervisor Logic
+                    with m.If(self.super_mode):
+                        # Valid if entry is not in user mode or supervisor
+                        # has Supervisor User Memory (SUM) access via the
+                        # SUM bit in the sstatus register
+                        m.d.comb += self.valid.eq((~self.data[4]) | self.super_access)
+                    # User logic
+                    with m.Else():
+                        # Valid if the entry is in user mode only
+                        m.d.comb += self.valid.eq(self.data[4])
+                with m.Else():
+                    m.d.comb += self.valid.eq(0)
+            with m.Else():
+                m.d.comb += self.valid.eq(0)
+        with m.Else():
+            m.d.comb += self.valid.eq(0)
+        return m
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