Correcting read/write port assignments

[soc.git] / TLB / src / TLB.py

diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py
index adf6b97121871e377fd365c106a20c08533593ff..aaa55da22cbad7b1838cba50a01496b1bbdc6701 100644 (file)
--- a/TLB/src/TLB.py
+++ b/TLB/src/TLB.py
@@ -55,8 +55,8 @@ class TLB():
             # Add submodules
             # Submodules for L1 Cache
             m.d.submodules.cam_L1 = self.cam_L1
-            m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port
-            m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.read_port
+            m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port()
+            m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.write_port()
             # Permission Validator Submodule
             m.d.submodules.perm_valididator = self.perm_validator