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Keep the valid signal from the formal engine ALU stable, until read
[soc.git]
/
conf.py
diff --git
a/conf.py
b/conf.py
index 12b29a4fb10659843b17c069255fcc3199cc77ba..d752f59ef042ac4b8d5f42bcebdf50308f0ee585 100644
(file)
--- a/
conf.py
+++ b/
conf.py
@@
-47,7
+47,7
@@
extensions = [
'sphinx.ext.coverage',
'recommonmark',
#'symbolator_sphinx',
- 'sphinxcontrib_verilog_diagrams',
+ #'sphinxcontrib_verilog_diagrams', # XXX now spinxcontrib-hdl-diagrams
'sphinx_rtd_theme',
#'sphinx_tabs.tabs',
]