# generate add.il ilang file with: python3 add.py
#
-from nmigen import Elaboratable, Signal, Module, Const, DomainRenamer
+from nmigen import (Elaboratable, Signal, Module, Const, DomainRenamer,
+ ClockSignal, ResetSignal)
from nmigen.cli import verilog
# to get c4m-jtag
from c4m.nmigen.jtag.tap import TAP, IOType
from nmigen_soc.wishbone.sram import SRAM
from nmigen import Memory
+from dummypll import DummyPLL
-class ADD(Elaboratable):
+class Core(Elaboratable):
def __init__(self, width):
self.width = width
self.a = Signal(width)
self.memsizes = []
#self.memsizes.append((32, 32)) # width, depth
self.memsizes.append((32, 16)) # width, depth
- self.memsizes.append((32, 16)) # width, depth
+ #self.memsizes.append((32, 16)) # width, depth
# create and connect wishbone(s). okok, a better solution is to
# use a Wishbone Arbiter, and only have one WB bus.
def elaborate(self, platform):
m = Module()
+ # create JTAG module
m.submodules.jtag = jtag = self.jtag
m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
return m
+class ADD(Elaboratable):
+ def __init__(self, width):
+ self.width = width
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.f = Signal(width)
+ self.jtag_tck = Signal(reset_less=True)
+ self.jtag_tms = Signal(reset_less=True)
+ self.jtag_tdi = Signal(reset_less=True)
+ self.jtag_tdo = Signal(reset_less=True)
+
+ # PLL input mode and test signals
+ self.a0 = Signal()
+ self.a1 = Signal()
+ self.pll_vco = Signal()
+ self.pll_test = Signal()
+
+ # QTY 1, dummy PLL
+ self.dummypll = DummyPLL(instance=True)
+
+ # core
+ self.core = Core(width)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ # create PLL module
+ m.submodules.wrappll = pll = self.dummypll
+
+ # connect up PLL
+ sys_clk = ClockSignal()
+ m.d.comb += pll.clk_24_i.eq(sys_clk)
+ m.d.comb += pll.clk_sel_i[0].eq(self.a0)
+ m.d.comb += pll.clk_sel_i[1].eq(self.a1)
+ m.d.comb += self.pll_vco.eq(pll.pll_vco_o)
+ m.d.comb += self.pll_test.eq(pll.pll_test_o)
+
+ # create core module
+ dr = DomainRenamer("coresync")
+ m.submodules.core = core = dr(self.core)
+
+ # connect reset
+ sys_rst = ResetSignal()
+ core_rst = ResetSignal("coresync")
+ m.d.comb += core_rst.eq(sys_rst)
+
+ # connect core from PLL
+ core_clk = ClockSignal("coresync")
+ m.d.comb += core_clk.eq(pll.clk_pll_o)
+
+ # and now the internal signals to the core
+ m.d.comb += core.a.eq(self.a)
+ m.d.comb += core.b.eq(self.b)
+ m.d.comb += self.f.eq(core.f)
+
+ # and to JTAG
+ m.d.comb += self.jtag_tdo.eq(self.core.jtag.bus.tdo)
+ m.d.comb += self.core.jtag.bus.tdi.eq(self.jtag_tdi)
+ m.d.comb += self.core.jtag.bus.tms.eq(self.jtag_tms)
+ m.d.comb += self.core.jtag.bus.tck.eq(self.jtag_tck)
+ return m
+
def create_verilog(dut, ports, test_name):
vl = verilog.convert(dut, name=test_name, ports=ports)
if __name__ == "__main__":
alu = DomainRenamer("sys")(ADD(width=4))
create_verilog(alu, [alu.a, alu.b, alu.f,
- alu.jtag.bus.tck,
- alu.jtag.bus.tms,
- alu.jtag.bus.tdo,
- alu.jtag.bus.tdi], "add")
+ alu.a0, alu.a1, # PLL mode
+ alu.pll_test, alu.pll_vco, # PLL test
+ alu.jtag_tck,
+ alu.jtag_tms,
+ alu.jtag_tdo,
+ alu.jtag_tdi], "add")