from nmigen.cli import rtlil
-from test_partsig import TestAddMod2
+from test_partsig import TestAddMod2, TestLS
import subprocess
import os
from nmigen import Signal
def test():
width = 16
pmask = Signal(3) # divide into 4-bits
- module = TestAddMod2(width, pmask)
- sim = create_ilang(module,
- [pmask,
- module.a.sig,
- module.b.sig,
- module.add_output,
- module.ls_output,
- module.sub_output,
- module.carry_in,
- module.add_carry_out,
- module.sub_carry_out,
- module.neg_output,
- ],
+ #module = TestAddMod2(width, pmask)
+ module = TestLS(width, pmask)
+ sim = create_ilang(module, [pmask] + module.ports(),
"part_sig_add")
def create_ilang(dut, ports, test_name):