import CRL
import Cfg
from Hurricane import Box
+from Hurricane import Transformation
from coriolis2.settings import af
from utils import Module, SessionManager, Config
def build(self):
h_margin = 25.0
- v_margin = 75.0
+ v_margin = 10.0
if not self.build_submodules():
return False
height = self.from_dbu(max([
self.ab.getHeight(), add.ab.getHeight(), sub.ab.getHeight()
])) + 2*v_margin
+
+ # experiment, over-ride
+ width = 1300
+ height = 370
+
self.ab = Box(0, 0, self.to_dbu(width), self.to_dbu(height))
- self.place_submodule(add, h_margin, v_margin)
- self.place_submodule(sub, width-sub.ab_width-h_margin, v_margin)
+ add_wid = self.from_dbu(add.ab.getWidth())
+ sub_ht = self.from_dbu(sub.ab.getHeight())
+ self.place_submodule(add, h_margin, v_margin+add_wid)
+ self.place_submodule(sub, width-sub.ab_width-h_margin+sub_ht-45,
+ v_margin)
# TODO: replace with some form of lazy evaluation?
y_north = self.from_dbu(self.ab.getYMax())
# this puts all the remaining cells (little ones)
# into this (small) space so that they do not go
# "all over the place" around the add and sub
+
+ # XXX this doesn't work: box is far too big, covers the entire
+ # area (including "under" the add and sub)
self.ab = Box(
self.to_dbu((width-self.ab_width)/2 - h_margin),
self.to_dbu(v_margin),
self.to_dbu((width+self.ab_width)/2 + h_margin),
self.to_dbu(height - v_margin)
)
- self.place()
+ self.ab = Box(self.to_dbu(450), self.to_dbu(15),
+ self.to_dbu(835), self.to_dbu(370))
+ self.place() # place only
# then route (globally)
# this connects up not just in the remaining (little) cells,
# it connects *to add and sub and the outside world as well*
self.ab = Box(0, 0, self.to_dbu(width), self.to_dbu(height))
- result = self.place_and_route()
+ result = self.route()
self.save()
return result
add = AddSub(
'add', editor,
north_pins=[
- {'net': 'a({})', 'x': 10.0, 'delta': 20.0, 'repeat': BIT_WIDTH},
- {'net': 'b({})', 'x': 20.0, 'delta': 20.0, 'repeat': BIT_WIDTH},
+ {'net': 'a({})', 'x': 165.0, 'delta': -10.0, 'repeat': BIT_WIDTH},
+ {'net': 'b({})', 'x': 160.0, 'delta': -10.0, 'repeat': BIT_WIDTH},
+ {'net': 'o({})', 'x': 340.0, 'delta': -10.0, 'repeat': BIT_WIDTH},
],
south_pins=[
- {'net': 'o({})', 'x': 100.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
],
pads={
'b({})'.format(BIT_WIDTH-1): (
'BLOCKAGE2', 'BLOCKAGE3', 'BLOCKAGE4',
),
},
+ orientation=Transformation.Orientation.R3,
)
sub = AddSub(
'sub', editor,
north_pins=[
- {'net': 'a({})', 'x': 10.0, 'delta': 20.0, 'repeat': BIT_WIDTH},
- {'net': 'b({})', 'x': 20.0, 'delta': 20.0, 'repeat': BIT_WIDTH},
+ {'net': 'a({})', 'x': 180.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
+ {'net': 'b({})', 'x': 185.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
+ {'net': 'o({})', 'x': 10.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
],
south_pins=[
- {'net': 'o({})', 'x': 100.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
],
pads={
'b({})'.format(BIT_WIDTH-1): (
'BLOCKAGE2', 'BLOCKAGE3', 'BLOCKAGE4',
),
},
+ orientation=Transformation.Orientation.R1,
)
alu16 = ALU16(
'alu16', editor, submodules=[add, sub],
north_pins=[
- {'net': 'o({})', 'x': 50.0, 'delta': 60.0, 'repeat': BIT_WIDTH},
+ {'net': 'o({})', 'x': 500.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
{'net': 'op'},
],
south_pins=[
- {'net': 'a({})', 'x': 50.0, 'delta': 60.0, 'repeat': BIT_WIDTH},
- {'net': 'b({})', 'x': 80.0, 'delta': 60.0, 'repeat': BIT_WIDTH},
+ {'net': 'a({})', 'x': 500.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
+ {'net': 'b({})', 'x': 700.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
],
west_pins=[
{'net': 'rst', 'y': 140.0, 'layer': 'METAL2'},